Dear Technical Support Team,
What is the timing of EN_smb?
Question 1:
What is the minimum pulse width when used as a Reset signal?
Question 2:
What is the minimum wait time until SMBus communication becomes available after setting Low->High?
We are planning to use the following flow
1. instruct FPGA to execute Reset on DS25CP104
2. the FPGA asserts EN_smb Low and initializes the DS25CP104 registers
3. return EN_smb to High
4. transfer various initial settings to DS25CP104 via SMBus
Question 1 is Low pulse width from 2 to 3,
Question 2 assumes a wait time from 3 to 4
Best Regards,
ttd