Hello TI team,
We are using the PHY DP83867 with RZG2UL, getting problem in enabling it in u-boot.
For that we have enabled, below u-boot configs
CONFIG_PHY=y CONFIG_PHY_TI=y CONFIG_PHY_TI_DP83867=y CONFIG_MII=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_FIXED=y CONFIG_CMD_NET=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BITBANGMII=y CONFIG_DM_ETH=y
And DTS node given below.
ð0 { pinctrl-0 = <ð0_pins>; pinctrl-names = "default"; phy-handle = <ðphy0>; phy-mode = "rgmii-id"; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; enet-phy-lane-no-swap; }; }; }; eth0_pins: eth0 { pinmux = <RZG2L_PINMUX(4, 3, 1)>, /* ET0_MDC */ <RZG2L_PINMUX(4, 4, 1)>, /* ET0_MDIO */ <RZG2L_PINMUX(1, 0, 1)>, /* ET0_TXC */ <RZG2L_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */ <RZG2L_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ <RZG2L_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ <RZG2L_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ <RZG2L_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ <RZG2L_PINMUX(3, 0, 1)>, /* ET0_RXC */ <RZG2L_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ <RZG2L_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ <RZG2L_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ <RZG2L_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ <RZG2L_PINMUX(4, 1, 1)>; /* ET0_RXD3 */ };
logs given below.
WDT: watchdog@0000000012800800 WDT: Started with servicing (60s timeout) MMC: sd@11c00000: 0, sd@11c10000: 1 Loading Environment from SPIFlash... SF: Detected at25sf321 with page size 256 Bytes, erase size 4 KiB, total 4 MiB OK In: serial@1004bc00 Out: serial@1004bc00 Err: serial@1004bc00 Model: sm2s-rzg2ul sm2s board late init... U-boot WDT started! Net: No ethernet found. Hit any key to stop autoboot: 0 => => => mii info PHY 0x00: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x01: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x02: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x03: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x04: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x05: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x06: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x07: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x09: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0A: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0B: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0C: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0D: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0E: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x0F: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x10: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x11: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x12: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x13: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x14: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x15: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x16: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x17: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x18: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x19: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1A: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1B: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1C: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1D: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1E: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x1F: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX => print ethaddr ethaddr=EA:17:DF:1B:EC:6A =>
Please guide us, how we enable the PHY in u-boot.
Thanks and regards.