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TCA4307: Solution if I can't use staggered connector in I2C hot-swap application.

Mohammad Medhat
Prodigy 50 points
Part Number: TCA4307
Other Parts Discussed in Thread: TCA9617B, TCA9511A

Peace be upon you all,

I want to use the I2C buffer "TCA4307" to get advantages from its features of hot insertion and rise-time acceleration. Although there are excellent information in the datasheets and documentation but still I have the following questions:

- What is the correct pulling resistor (Rp) to provide rise time 120 ns at 3.3 DC and 1 MHZ I2C speed (FM+)? From the curve figure 8-4 in the datasheets, the Rp is 1 Kohm for 20 ns rise-time so, I believe I can use the same value which exceeds the FM+ requirements.


- In case I can't implement the staggered connector to ensure the sequence connection of GND -> VCC -> SDAIN, SCLIN, then can we put a capacitor and resistance (for example: 47 Kohm, 0.1 uf) on the "EN" pin of "TCA4307" to ensure the chip will not connect the I2C buses (IN and OUT) until the VCC is connected and stable?

Thanks.


  • +1
    TI__Guru 50688 points

    Hi Mohammad,

    Mohammad Medhat said:

    - What is the correct pulling resistor (Rp) to provide rise time 120 ns at 3.3 DC and 1 MHZ I2C speed (FM+)? From the curve figure 8-4 in the datasheets, the Rp is 1 Kohm for 20 ns rise-time so, I believe I can use the same value which exceeds the FM+ requirements.

    This can be determined by following the calculation in the app note here. This app note assumes that the pull-up resistor is the only component in the rising edge transition. TCA4307 adds in pull-up current from the rise-time accelerator (RTA), which provides a typical 5mA of pull-up current when Vsda/scl = 0.6V and VCC = 3.3V. 

    If the pull-up calculation is made without consideration of the RTA, then you are guaranteed by design that you will reach the standard for FM+ I2C speeds if you follow the calculation in the app note without consideration for RTA.

    Mohammad Medhat said:
    - In case I can't implement the staggered connector to ensure the sequence connection of GND -> VCC -> SDAIN, SCLIN, then can we put a capacitor and resistance (for example: 47 Kohm, 0.1 uf) on the "EN" pin of "TCA4307" to ensure the chip will not connect the I2C buses (IN and OUT) until the VCC is connected and stable?

    The GND connection first is vital for hot-plug systems and should be the last disconnected (by design). Capacitance would not have the same affect. The staggered connection is useful in that is helps prevent any potential back biasing through SDA/SCL lines if they connect first. Back biasing could potentially damage surrounding circuitry this way. 

    For more reference please see this app note regarding I2C hot-swap applications

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Hi Tyler,

    Thanks for your reply and explanations.

    For the Rp question, I calculated the Rp based on the information in the app note you mentioned and it will be small resistor as expected. I want to take advantage from the rise time accelerator of the TCA4307 but I couldn't find a similar equation as it is exist in the app note. The datasheet of TCA4307 only provided the curves which indicates that Rp = 1Kohm is suitable up to 20 ns rise time. Although 20 ns is exceeding the FM+ 1MHZ I intend to use but I think I have no choice but to use it because there is no other equations to calculate exact Rp for the 1 MHZ rise time.

    So, as a conclusion, I can use the 1Kohm with TCA4307 for the FM+ 1MHZ speed without problems.

    For the staggered connector point ... Thank you for explaining the "back biasing" point. I understand now and I have to find a staggered connector. The problem is that I'm using a ready connector (not PCB edge connector) and it comes not ready for hot-swap application. I will try to contact the manufacturer may be they have a solution.

    Regards,

    Mohammad.

  • 0 in reply to Mohammad Medhat
    Guru 318050 points

    The TCA4307 is not guaranteed to support any speed higher than 400 kHz, regardless of what resistors you use.

  • 0 in reply to Clemens Ladisch
    Prodigy 50 points

    Hi Clemens,

    I noticed that there is no other buffer supporting FM+ and also the curve in TCA4307 datasheet indicated the 20 ns rise time and mentioned the 400KHZ as "minimum speed" so I thought the TCA4307 is working in FM+ otherwise they should develop new ICs for the higher speed!

    I hope there is more details on the internals of TCA4307 to understand how it works and what is the relation between the specified rise time and the Rp? Is the internal current source affected by the external Rp in generating the charging current or it is only when the 0.6 V reached faster then the overall rise time is faster. Also, I wonder what is the benefits of having 20 ns rise time at 400 KHZ?

    What if I tested TCA4307 at 1MHZ and it worked then can I use it safely in the project or still other chips may not work?

    Regards,

    Mohammad.

  • 0 in reply to Mohammad Medhat
    Guru 318050 points

    The curve in the TCA4307 datasheet is copied from somewhere else. (Where is footnote 2?) A rise time of 20 ns would not make sense for a fast-mode bus.

    The value in section 6.5 is the maximum clock frequency. The value of 400 kHz is in the "minimum" column because this value is guaranteed for all devices under all circumstances. Some chips, at some temperatures, might be able to go higher, but those cannot be guaranteed.

    There is no FM+ solution with all the features that you want.

  • 0 in reply to Mohammad Medhat
    TI__Guru 50688 points

    Mohammad,

    Sorry for the misunderstanding. TCA4307 is only guaranteed to 400kHz operation, Clemens is correct here. 

    Device electrical characteristics cannot be guaranteed by the datasheet at 1 MHz. FM+ operation on the TCA4307 may or may not work as expected. 

    Our only fast mode buffer is the TCA9617B. It does not have features such as hot-swap capability, stuck bus detection, pre-charge. It is a standard I2C buffer with static voltage offset on the B-side, but is characterized for 1 MHz. 

    1MHz hot-swap might be able to be done discretely using TCA9617B + MUX + TCAL IO expander. See figure 3-1 from the discrete hot insertion implementation of the hot swap app note.

    Mohammad Medhat said:
    I hope there is more details on the internals of TCA4307 to understand how it works and what is the relation between the specified rise time and the Rp? Is the internal current source affected by the external Rp in generating the charging current or it is only when the 0.6 V reached faster then the overall rise time is faster. Also, I wonder what is the benefits of having 20 ns rise time at 400 KHZ?

    The RTA is like a FET that is turned ON during the transition from a Low logic period to a high logic period. It looks effectively like a pull-up resistor.

    From the datasheet, if VCC = 3.3V, typical IPU = 5mA, and VSDA/SCL = 0.6V, we can calculate what the "Rpull-up" strength would be of this RTA. 

    R = (3.3V - 0.6V) / 5mA = 540ohms

    The pull-up strength of the RTA looks like a 540 ohm pull-up resistor. Anything added in parallel externally to this would make the total pull-up resistance smaller (stronger pull-up). 

    RTA triggers at 0.6V and when the slew rate is at least 1.25 V / us. In my bench test for this part, I was able to comfortably operate the TCA4307 with 20kohm pull-up resistors on both sides due to the built in RTA's that assist on the rising edge. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Thanks Clemens for correcting my understanding. I think really the datasheet curve is not correct.

    And many thanks Tyler for your explanation. So, it is a normal capacitor charging through current source ranging from 2 to 5 mA which exceeds the fast mode requirements (400 KHZ at 400 pf) starting from 4 mA charging current.

    You said that you tested the TCA4307 with 20kohm pull-up resistors, so I understand it worked fine on 400 KHZ but you didn't test on higher speeds such as 1 MHZ.

    I don't know if it is applicable to you to test with 1 MHZ speed. With 3 to 5 mA current source it is supposed to work on 1MHZ up to 200 pf load capacitance.

    Regards,

    Mohammad.

  • 0 in reply to Mohammad Medhat
    TI__Guru 50688 points

    Mohammad,

    The i2c standard states:

    More of a timed FET circuit that turns ON and OFF depending on voltage threshold and slew rate. 

    Mohammad Medhat said:
    You said that you tested the TCA4307 with 20kohm pull-up resistors, so I understand it worked fine on 400 KHZ but you didn't test on higher speeds such as 1 MHZ.

    The device from a datasheet perspective is only rated for standard mode and fast mode. 0 kHz to 400kHz is the recommended speeds. Any speed higher is outside datasheet characteristics. The device is not tested for speeds >400kHz, although the device may work faster than what is guaranteed in the datasheet. 

    Mohammad Medhat said:
    I don't know if it is applicable to you to test with 1 MHZ speed. With 3 to 5 mA current source it is supposed to work on 1MHZ up to 200 pf load capacitance.

    The device is only characterized to 400kHz. This is a true I2C hot-swap buffer capable of separating two segments of the i2c able to drive 400pF on the input and 400pF of load cap on the output for a total of 800 pF --> I.e. buffer separates the i2c bus into segments by re-driving the bus. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Thanks Tyler, I understand.

    I decided to operate at 400 KHZ because the discrete solution using TCA9617B + MUX + TCAL IO expander is not applicable in my case. The design is based on DIN-rail modules (<25) connected side by side by right and left connectors in each module and it is not a fixed backplane where each card can have its own I2C bus through switch or MUX. The maximum distance to the last module is about 50 cm which by calculations + input capacitance of TCA4307 is within 400 pf.

    Please let me comeback again to the hot-swap point.

    In the hot-swap application note page 3 it mentioned the following:

    Additional notes:
    • The external card should connect GND and then power before SDA/SCL:
    – This helps prevent any potential back biasing through the SDA/SCL lines if they connect first.
    – Requires a female to male connector which staggers the signals to connect at different times.

    And in page 4 repeated again:

    The second design set up required is the connection from the external card to the backplane must connect the ground and power to the external card first before the SDAIN/SCLIN connects to the backplane I2C bus.

    The reason for this is the TCA9511A needs to power up and turn on its 1-V pre-charge circuit before the SCLIN/SDAIN connects to the backplane. If the SDAIN or SCLIN lines connect to the backplane at the same time as the power and ground, then the 1-V pre-charge circuit do not power up in time and the backplane I2C bus may dip down towards ground momentarily if the SDA/SCL lines on the backplane are HIGH or transitioning HIGH.

    And in figure 8-6 in the TCA4307 datasheet, the sequence of the connections according to the staggered connector is: GND then VCC then SDA/SCL then BD_SEL.

    The BD_SEL is connected to the hot-swap power supply on the external card. The output of the hot-swap power supply is powering the TCA4307 not the main VCC.

    So even if the GND and VCC connected to the board before the SDA/SCL but still the hot-swap supply is not activated yet and the TCA4307 is not powered yet. i.e it is only the GND then the SDA/SCL is connected to the TCA4307 before the actual power of TCA4307 which comes from the output of the hot-swap power supply.

    Also, usually the hot-swap power supply will take a time to ramp-up the output voltage.

    So, if I understand correctly, then my question is, will GND be enough to prevent any back biasing on the TCA4307 and also preventing pulling the SDA/SCL lines to GND while it is high?

    I think also the back-biasing issue is due to the FET which may be connected before the TCA4307 is powered up. The FET need to be disconnected after the TCA4307 is powered up. Do I understand correctly?

    Regards,

    Mohammad.

  • 0 in reply to Mohammad Medhat
    Prodigy 50 points

    Just to clarify that, although it is 24 modules + the master but it will be divided into two I2C busses, 16 modules on one bus and 8 on another bus. The TCA4307 will buffer all I2C slaves on each module so the overall bus capacitance per each I2C bus is less than 400 pf.

    Any comments regarding this connection scheme feasibility are welcomed and appreciated.

  • 0 in reply to Mohammad Medhat
    TI__Guru 50688 points

    Hi Mohammad,

    Mohammad Medhat said:
    So even if the GND and VCC connected to the board before the SDA/SCL but still the hot-swap supply is not activated yet and the TCA4307 is not powered yet. i.e it is only the GND then the SDA/SCL is connected to the TCA4307 before the actual power of TCA4307 which comes from the output of the hot-swap power supply.

    The in-rush currents of improper grounding needs to be avoided. Although a low power application like this one using I2C, it is still good practice to have staggered connections. In-rush currents could damage the IO's if GND'ing is not establish first and removed last. A floating GND connection is not good even in low-power systems. 

    Mohammad Medhat said:
    So, if I understand correctly, then my question is, will GND be enough to prevent any back biasing on the TCA4307 and also preventing pulling the SDA/SCL lines to GND while it is high?

    BD_SEL seems to be an added layer of protection when supplying VCC to the TCA4307. 

    Floating GND is not ideal even if BD_SEL is present. In-rush currents most likely would exist without GNDing being the first and last connection of the peripheral card. 

    Mohammad Medhat said:
    I think also the back-biasing issue is due to the FET which may be connected before the TCA4307 is powered up. The FET need to be disconnected after the TCA4307 is powered up. Do I understand correctly?

    What FET are you referring to here? 

    Mohammad Medhat said:

    Just to clarify that, although it is 24 modules + the master but it will be divided into two I2C busses, 16 modules on one bus and 8 on another bus. The TCA4307 will buffer all I2C slaves on each module so the overall bus capacitance per each I2C bus is less than 400 pf.

    Any comments regarding this connection scheme feasibility are welcomed and appreciated.

    This connection scheme seems okay as long as each module has its own unique I2C address, and the parasitic bus cap does not exceed 400pF each side of the TCA4307... the SDA/SCL IN side and the SDA/SCL OUT side totaling for 800pF of parasitic bus cap load. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Hi Tyler,

    The FET I meant which you mentioned before in earliest reply:

    "The RTA is like a FET that is turned ON during the transition from a Low logic period to a high logic period. It looks effectively like a pull-up resistor."

    The idea is that .. when the TCA4307 is powered off it is supposed to show a high-Z on the SDA/SCL so we can easily put a capacitor to GND and resistor to VCC on the "EN" pin TCA4307 to prevent any load effect on the I2C bus until the TCA4307 is fully powered and take control to safely connect the SDA/SCL to the I2C bus on both sides. Unfortunately it seems that this is not what happen and TCA4307 is loading the I2C bus while it is not powered up maybe due to some internal component.

    On the other hand, figure 8-6 in the datasheet violates the hot-swap application note by connecting SDA/SCL before TCA4307 powered up through the hot-swap power supply on the external card.

    The question here is: did TI team tested TCA4307 according to figure 8-6 and it worked without loading the I2C bus? if the answer is yes then mostly TCA4307 is isolating the SDA/SCL as high-Z while it is not powered up hence no need for the staggering connector. Maybe only GND could be connected first to prevent floating GND on the external card.

    I hope my point is clear.

    Regards,

    Mohammad.

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Hi Tyler,

    Tyler Townsend said:
    This connection scheme seems okay as long as each module has its own unique I2C address, and the parasitic bus cap does not exceed 400pF each side of the TCA4307... the SDA/SCL IN side and the SDA/SCL OUT side totaling for 800pF of parasitic bus cap load. 

    Yes, everything will be as you mentioned above and we will use 1Kohm pullup on the IN side which will provide best rise time on >400KHZ/400 pf I2C and sink current of about 3 mA on 3.3V supply.

    Regards,

    Mohammad.

  • 0 in reply to Mohammad Medhat
    TI__Guru 50688 points

    Mohammad,

    Yes I see your point. I think the figure 8-6 typical application is somewhat misleading since we explicitly say that GND > VCC > SDA/SCL is the order in which signals should connect. There is no explanation to what signal BD_SEL is doing. If BD_SEL = HIGH and it turns on the power supply to the hot-swap then the staggered connections would be appropriate. Otherwise, it is misleading in the diagram. 

    Mohammad Medhat said:
    The idea is that .. when the TCA4307 is powered off it is supposed to show a high-Z on the SDA/SCL so we can easily put a capacitor to GND and resistor to VCC on the "EN" pin TCA4307 to prevent any load effect on the I2C bus until the TCA4307 is fully powered and take control to safely connect the SDA/SCL to the I2C bus on both sides. Unfortunately it seems that this is not what happen and TCA4307 is loading the I2C bus while it is not powered up maybe due to some internal component.

    I was reading the app note

    https://www.ti.com/lit/an/slva703/slva703.pdf?ts=1708035284850&ref_url=https%253A%252F%252Fwww.google.com%252F

    Regardless of the plan to put a cap to GND and resistor to VCC on EN of TCA4307. Whether TCA4307 is powered up to VCC or GND'ed, the major concern is the diode facing from GND to pin. I believe that this is the source of hot-swap problems which is why connecting common GND is important, otherwise there could be significant inrush current that could damage this GND to pin diode causing a permanent short to the IO pin. 

    I don't believe there are pin to VCC ESD diodes present in the TCA4307. Regardless, there is some ESD structure in the TCA4307 that if GND at least is not established first, there could be consequences to the device. There is no way for me to tell from a datasheet perspective what this line is to when you are guaranteed safe for hot-plug without staggered connection vs. when damage would occur to the IC or some device in the system. 

    Mohammad Medhat said:
    The question here is: did TI team tested TCA4307 according to figure 8-6 and it worked without loading the I2C bus? if the answer is yes then mostly TCA4307 is isolating the SDA/SCL as high-Z while it is not powered up hence no need for the staggering connector. Maybe only GND could be connected first to prevent floating GND on the external card.

    I have not tested the 4307 according to figure 8-6. 

    Even if SDA/SCL are high-Z while the device is not powered up, the in-rush current from the inductance from the backplane supply into the parasitic cap of the TCA4307 creates a possibility for over-voltaging the IO pins. Abs. max voltage input is -0.5V to 7V, not much margin here for absolute protection from damage in a hot-plug scenario. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Hi Tyler,

    Thanks for the application note about transients in hot-swap. It is an excellent work explained to me a lot of what I couldn't understand before.

    Tyler Townsend said:
    Even if SDA/SCL are high-Z while the device is not powered up, the in-rush current from the inductance from the backplane supply into the parasitic cap of the TCA4307 creates a possibility for over-voltaging the IO pins. Abs. max voltage input is -0.5V to 7V, not much margin here for absolute protection from damage in a hot-plug scenario.

    If we agree that we have to apply the GND first anyway to the hot-swap card then the main concern is what it is mentioned in the TCA4307 datasheet and the I2C hot-swap AN the concern on the SDA/SCL is related to the bus interruption when the bus is high and TCA4307 SDA/SCL suddenly connected to the bus because it may pull it down causing a missed clock to the slave communicating at that time with the master. So, it is required that the TCA4307 powered up first to apply the 1-V pre-charge before properly connecting sides IN and OUT together while the I2C bus is idle or after stop bit detected on the IN side.

    So, in case TCA4307 shows high-Z on I2C bus while it is not powered then everything will be fine if we just followed the sequence indicated in figure 8-6. I.e, connect GND first then whatever come next is not a problem.

    So, can you investigate this point (may be internally with TI designers):

    "Does TCA4307 shows high-Z on I2C bus while it is not powered?"

    I believe answering the above question should resolve this issue with appreciation and thanks Slight smile

    Regards,

    Mohammad.

  • +1 in reply to Mohammad Medhat
    TI__Guru 50688 points

    Hi Mohammad,

    I believe I understand your point now. 

    Mohammad Medhat said:

    If we agree that we have to apply the GND first anyway to the hot-swap card then the main concern is what it is mentioned in the TCA4307 datasheet and the I2C hot-swap AN the concern on the SDA/SCL is related to the bus interruption when the bus is high and TCA4307 SDA/SCL suddenly connected to the bus because it may pull it down causing a missed clock to the slave communicating at that time with the master. So, it is required that the TCA4307 powered up first to apply the 1-V pre-charge before properly connecting sides IN and OUT together while the I2C bus is idle or after stop bit detected on the IN side.

    So, in case TCA4307 shows high-Z on I2C bus while it is not powered then everything will be fine if we just followed the sequence indicated in figure 8-6. I.e, connect GND first then whatever come next is not a problem.

    So, can you investigate this point (may be internally with TI designers):

    "Does TCA4307 shows high-Z on I2C bus while it is not powered?"

    This statement in the datasheet helps to answer your question:

    Please let me know if you have any further questions. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 50 points

    Hi Tyler,

    Yes, this is what I meant because it is mentioned in page 1 of the datasheet as follows:

    But when they mentioned it again in page 10 and we started our discussion I got confused that it may be Hi-Z only when the IC is powered but detected the UVLO not when it started with zero volt Vcc.

    I hope now I well understand the IC and how to connect it for best utilization of its nice features.

    Many thanks for your support, explanations and good information. It is highly appreciated.

    Thanks also for Clemens for his support.

    Regards,

    Mohammad.