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Original question:

P82B715: P82B715 design feasiblity

P82B715: Using Two P82B715 To Resolve Vol Issue

Matthew Nordeen
Prodigy 60 points
Part Number: P82B715
Other Parts Discussed in Thread: TCA9800, P82B96, PCA9306

We do not have a long cable or high bus capacitance, but we are considering using two P82B715 devices to solve two other issues in our design:

1. The Vol driven by some of our I2C slaves is not low enough for our host to recognize the low level.  We need Vol to be 0.4V or less.

2. Our host and slaves are both operating at 3.3V, but the host power comes up prior to the slave power.  Therefore, we would like to have an isolator such as the FXMAR2102UMX (https://www.onsemi.com/products/timing-logic-memory/standard-logic/level-translators/FXMAR2102) installed between two P82B715 devices.

Design concept:

Can we use the devices this way reliably?  Do you have any suggestions on how we could solve our two issues?

Thank you,

Matt

  • 0
    Guru 311760 points

    The P82B715 increases current, but it cannot reduce VOL. (Neither can the FXMAR2102, which is a passive switch.)

    To reduce VOL, you need an I²C buffer like the TCA9800/1/2/3.

    (The simplest way to reduce VOL is to increase the pull-up resistance; this might require reducing the speed.)

  • 0
    TI__Mastermind 42403 points

    Hi Matt,

    Considering that you do not have a need for buffering high bus cap, or are using long cabling, the P82B96 seems excessive especially when paired with the FXMAR2102. 

    To answer question 1, Clemens suggested the most simple way to reduce VOL and that is to change Rpull-up to a larger resistance which will reduce VOL but in turn increase rise-time on the bus. 

    Matthew Nordeen said:
    Can we use the devices this way reliably?  Do you have any suggestions on how we could solve our two issues?

    I am thinking a simple level translator would work here. A device such as the PCA9306 does not have power sequencing requirements, i.e. VREF1 can be powered first while the slave device power comes up second (VREF2). 

    A design like this might work...

    Pardon my rough drawing skills but I hope you get the picture. V_A comes up first, so the PCA9306 would be disabled since EN is connected to the V_B node. Once V_B is powered up, PCA9306 will be active. 

    VOL across PCA9306 will be very low due to the passivity of this device. Host VOL will be a RON voltage drop higher at the I2C target side. 

    See datasheet here PCA9306. 

    Regards,

    Tyler