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DP83867IS: CLK_OUT: Receive clock if there is no link?

Part Number: DP83867IS


I'm currently configuring my ethernet PHY to output the receive clock divided by 5, resulting in 25 MHz on a 1Gbit/s link.

Using a logic analyzer I could verify the write sequence as follow:

  1. Reg_0x0D=0x001F
  2. Reg_0x0E=0x0170
  3. Reg_0x0D=0x401F
  4. Reg_0x0E=0x40F

This actually results in a clock output pf 25 MHz.

But I am wondering why I do still get a 25 MHz clock if there is no link and the PHY is configured as link slave (Register 0x9 set to 0x1300).
I would have expected to see no clock output if there is no receive clock. Could someone clarify how can I verify I get the ethernet switch clock.

Thanks and best regards,