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Original question:

DS90UB638-Q1: Design documents support for DS90UB638-Q1

DS90UB638-Q1: Output driver structure

Barry W
Intellectual 840 points
Part Number: DS90UB638-Q1

We are going through an FMEA (Failure Mode & Effects Analysis) on our system that implements the DS90UB638-Q1.

Of particular concern deep in this analysis is the backchannel output of the RIn0+ pin.

Can you share any details the output driver / input buffer structure of this pin?  

It might also be helpful to analyze the structure of the CSI output pins and their relationship to the RIN0 pins if that is available.

The top level concern is that unintentional energy on the CSI output pins could find its way to the RIn0- pin and be switched out at 25MHz, providing significant AC energy on the coax.

I'm confident this is not actually possible, but we could sure use some sort of evidence that this could never happen to complete our analysis.

We have an existing NDA with TI initiated by another product group if that is helpful.

Thanks

  • 0
    TI__Genius 14700 points

    Hi Barry,

    Let me look into this.

  • 0 in reply to Glenn Uranga
    TI__Mastermind 19931 points

    Hi Barry,

    Could you please help to point me to the specific lines in the FMEA which you're concerned about? There are some specific details about our design which we cannot share but I will do my best to answer questions about the line items of concern.

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    Intellectual 840 points

    Hello, Thomas,

    We are only concerned with output of the RIN0+ pin, because it is the only pin connected to the remote sensor coax cable.

    The failure modes are all potential signal shorts outside and inside the 638.  The effect is delivering unsafe energy out the coax connection.  The controls are current limits to most of the 638 pins.

    We are only concerned with AC signals coming out of RIN0+.  Any DC energy will be blocked by the external capacitor connected to RIN0+.

    We can current limit all the connections to the 638 except the 10 CSI output pins.  These pins are connected directly to an SoC.  Power to the SoC is not limited and if a short occurred, it could provide energy across the CSI pins that exceed our limits if it were switched to an AC waveform.

    It seems there could be ESD structures on the 638 CSI output pins that could transfer a voltage to other parts of the 638.  It seems possible (however unlikely) that the RIN0+ output driver could switch that energy at <=25MHz onto the RIN0+ pin at currents exceeding the data-sheet specification for normal operation.

    If you can provide any sort of evidence that this scenario is not possible, it would greatly help our analysis and product design.

    Thanks

  • 0 in reply to Barry W
    TI__Mastermind 19931 points

    Hi Barry,

    Let me check with my team on this specific failure mode, will get back to you shortly.

    Best,

    Thomas