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DS90UB947-Q1: I2C Pass Through All on ds90ub947-q1 and ds90ub948-q1

Part Number: DS90UB947-Q1
Other Parts Discussed in Thread: DS90UB948-Q1, ALP

Hello, I am having a project that uses ds90ub947-q1 and ds90ub948-q1. I am using I2C Pass Through All function for ds90ub947-q1 and ds90ub948-q1. But I am having a problem with configurating for ds90ub948-q1 (via I2C). I set bit 7 of register 0x17(I2C Control) is 1 to enable I2C Pass Through function in ds90ub97-q1 and I also confirm that this bit is set by reading value of register 0x17 again. After I set I2C Pass Through All for ds90ub947, I continue to configure for ds90ub948-q1 via I2C but I can't do that because seem that I2C Pass Through All in ds90ub947-q1 is abnormal action. Sometimes I can read value of a ds90ub948-q1's register but usually it will give an error. I also read https://www.ti.com/lit/an/snla222/snla222.pdf about I2C Pass Though All function. What any things I must do more to this function to it is normal action?

Wish to receive your help soon!

  • Hi Quan,

    What any things I must do more to this function to it is normal action?

    What is your setup? Are you using an EVM with ALP? In order to get remote I2C communication to the 948, valid lock and I2C pass through must be present. Either the PATGEN needs to be running or video input needs to be applied to generate the forward channel communication.

    Sometimes I can read value of a ds90ub948-q1's register but usually it will give an error

    Can you show me what the error looks like?

    Best,

    Jack

  • I read value of register 0x27 of ds90ub948-q1 periodically 10ms. It return I2C timeout error (I think because of not receiving bit ACK), however sometimes it also return a notify that read via I2C is OK and read value of register is 0x84 (default value of register 0x27). I retry with reading another register and it's same (sometimes it return correct default value of register). I see it's operation is quite unstable. Picture below is a part my system

  • Hi Quan,

    Thank you for the diagram. If the registers are not returning consistent values, this means the link is possibly unstable. Are you able to monitor the lock status on the 948 side? Can you also provide a register dump of the 947 so we can see if there are CRC errors or link loss detection?

    Best,

    Jack

  • Hi Jack,

    Thank for your response!

    I can't check status of LOCK pin on 948 because reason relating to system construct. Below is value of registers on 947 that I read after config by I2C

    Reg 0x00: 0x34

    Reg 0x03: 0xD0

    Reg 0x04: 0x90

    Reg 0x05: 0x00

    Reg 0x06: 0x58

    Reg 0x0D: 0x21

    Reg 0x0E: 0x11

    Reg 0x0F: 0x01

    Reg 0x10: 0x03

    Reg 0x11: 0x00

    Reg 0x12: 0x00

    Reg 0x14: 0x00

    Reg 0x17: 0x9E

    Reg 0x18: 0x0B

    Reg 0x19: 0x1F

    Reg 0x1A: 0x01

    Reg 0x4F: 0xC0

    Reg 0x5B: 0x20

    Reg 0xC6: 0x21

  • Hi Quan,

    We will need to see the 947 status registers in order to determine if the link is unstable. Can you read the following registers?

    • 0xA & 0xB - CRC Errors
    • 0xC - General Status
    • 0x5A - Dual status

    Try reading 0xC multiple times to see if the value changes due to link detection or an invalid PCLK.

    Best,

    Jack

  • Hi Jack,

    I will read value of registers that you required soon and feedback you after. Now, I'm having a question about I2C Clock stretching in 947. Is there any way to configure I2C Clock stretching mode for 947?

  • Hi Quan,

    The I2C controller built into the 947 automatically supports clock stretching. The MCU for your system must support I2C clock stretching.

    Best,

    Jack

  • Hi Jack,

    Thanks for your response about I2C Clock Stretching. So, is there any note about value SCL High Time and SCL Low Time register? If I2C clock of my host MCU is about 400kHz, what value that I should set for these registers?

  • Hi Quan,

    I can see from the register configuration of registers 0x18 and 0x19 that the fast mode (400kHz) speed has already been configured. The minimum low and high periods match the I2C specification. These registers only control the I2C speed when the 947 acts as the I2C master on the bus. When the MCU drives the I2C bus, the 947 will accept different I2C clock speeds without prior register configuration.

    Best,

    Jack

  • Hi Jack,

    You can explain more for me about when the 947 acts as the I2C master on the bus is? I don't really understand this place. If you are not bothered, could you give a example system?

  • "The I2C controller built into the 947 automatically supports clock stretching" 948 is like that, right?

  • Hi Quan,

    You can explain more for me about when the 947 acts as the I2C master on the bus is?

    When the MCU connected to the local 947 I2C bus initiates a transaction, the 947 is the slave on the I2C bus. If an MCU or other controller on the DES side reads/writes from the MCU on the 947 bus, the 947 will act as the I2C master.

    In order to allow bidirectional I2C communication across the remote link, the FPD-Link I2C module can act as both master and slave if needed.

    "The I2C controller built into the 947 automatically supports clock stretching" 948 is like that, right?

    Yes.

    Have you read the registers I mentioned eariler?

    Best,

    Jack

  • Hi Jack,

    These are value of registers that you required

  • Hi Quan,

    Thank you for capturing the registers. Registers 0xA and 0xB are the CRC counter for the back channel. I can see that it is incrementing significantly indicating link issues. This is why the remote I2C transactions are not consistent. What type of cable are you using for the FPD-Link channel?

    Are you enabling the PATGEN on the 947? I see from register 0xC and 0x5A there is no oLDI input detected.

    Best,

    Jack

  • Hi Jack,

    I'm using twisted-pair cable. How I can enable PATGEN on the 947? At present, I'm config for 947 and 948 before providing LVDS signal for them. And seem that this is make my 947 and 948 work unstably, right?

  • Hello Quan,

    please refer to the below Application note:

    www.ti.com/.../snla132g.pdf

  • Okay. Thanks for your help, Jack, Hamzeh!!!!

  • Hi Jack and Hamzeh,

    I read reg 0x5A of 947 and see that bit 7 of this reg is unstable. What are the reasons leading to this?

    Please help me!!!

  • Hello Quan,

    is your connection between SER and DES stable? Do you see stable LOCK on the DES side?

  • Yes, it  is. And I see that LOCK pin is unstable

  • Hello Quan,

    The US team is currently out of office due to the US public holiday and will return on 5/28. Thank you for your patience at this time 

    Best Regards,

    Casey

  • Hi Quan,

    Thank you for your patience. Severe weather has cut power in Dallas so my responses have been delayed.

    At present, I'm config for 947 and 948 before providing LVDS signal for them.

    LVDS signal is recommended to be provided as the final step of the power on sequence. I can provide a script tomorrow that can program the 947 PATGEN if you are unable to apply the LVDS signal. Without the LVDS signal, the 947-948 link will not be sufficient. The LVDS clock input is required for system operation.

    Best,

    Jack

  • Hi Jack,

    I wait your script tomorrow!!!

  • Hi Quan,

    Attached is the 947 PATGEN script. It is configured for 720p timing. Lock should be established after running the script.

    Best,

    Jack

    947_PATGEN.txt
    board.WriteI2C(0x18, 0x64, 0x00)    #   Disable PATGEN
    board.WriteI2C(0x18, 0x66, 0x03)
    board.WriteI2C(0x18, 0x67, 0x03)    #   PATGEN_CDIV_N		
    board.WriteI2C(0x18, 0x66, 0x04)		
    board.WriteI2C(0x18, 0x67, 0x70)    #	THW_7:0
    board.WriteI2C(0x18, 0x66, 0x05)		
    board.WriteI2C(0x18, 0x67, 0xE6)    #	TVW_3:0
    board.WriteI2C(0x18, 0x66, 0x06)		
    board.WriteI2C(0x18, 0x67, 0x2E)    #	TVW_11:4
    board.WriteI2C(0x18, 0x66, 0x07)		
    board.WriteI2C(0x18, 0x67, 0x00)    #	AHW_7:0
    board.WriteI2C(0x18, 0x66, 0x08)		
    board.WriteI2C(0x18, 0x67, 0x05)    #	AVW_3:0
    board.WriteI2C(0x18, 0x66, 0x09)		
    board.WriteI2C(0x18, 0x67, 0x2D)    #	AVW_11:4
    board.WriteI2C(0x18, 0x66, 0x0A)		
    board.WriteI2C(0x18, 0x67, 0x50)    #	HSW_7:0
    board.WriteI2C(0x18, 0x66, 0x0B)		
    board.WriteI2C(0x18, 0x67, 0x05)    #	VSW_7:0
    board.WriteI2C(0x18, 0x66, 0x0C)	
    board.WriteI2C(0x18, 0x67, 0xD8)    #	HBP
    board.WriteI2C(0x18, 0x66, 0x0D)		
    board.WriteI2C(0x18, 0x67, 0x16)    #	VBP
    board.WriteI2C(0x18, 0x66, 0x0E)		
    board.WriteI2C(0x18, 0x67, 0x00)    #	VS_POL
    board.WriteI2C(0x18, 0x66, 0x1A)
    board.WriteI2C(0x18, 0x67, 0x01)    #   PATGEN_CDIV_M
    board.WriteI2C(0x18, 0x65, 0x04)    #	Internal timing
    board.WriteI2C(0x18, 0x64, 0x11)	

  • Hi Jack,

    Thanks for your help. My system could display on the monitor now. But I still have a question about register 0x28 of 948, I try set bit1 of it is 1 but when I read it after written this bit it still is 0 (other bits of register 0x28 can be set normally)

  • Hi Quan,

    Register 0x28 (DATAPATH_CONTROL_2) requires that bit 7 be asserted to change any of the other bits in this register. Are you asserting bit 7 when trying to overwrite the other bits?

    Normally, this register does not need to be manually written because it receives the appropriate info from the upstream serializer.

    Best,

    Jack

  • Okay! Thank you so much Jack. That's lucky when receive your help!

  • Hi Quan,

    Happy to help. If you have any further questions, you can reply here or start a new thread. I recommend starting a new thread if you have a question/issue that is unrelated to this conversation.

    Best,

    Jack