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THVD4431: PLASTIC QUAD FLATPACK for QFN-40 pin

dimitry chen
Expert 1105 points
Part Number: THVD4431

Tool/software:

Hi

 I am writing to inquire about the different package designs for the QFN-40 pin

I have found three different package designs in:

  • RHA0040H
  • RHA0040C
  • RHA0040R

Could you please provide me with more information about the differences in design requirements between these packages?

ex . gnd via number and  thermal pad size ?

https://www.ti.com/lit/ds/symlink/dac8234.pdf?ts=1716957959717&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US

RHA0040H

https://www.ti.com/lit/ds/symlink/lmx1214.pdf?ts=1716958185543&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US

RHA0040C

https://www.ti.com/lit/ds/symlink/thvd4431.pdf?ts=1716944651014

RHA0040R

  • 0
    TI__Guru 62930 points

    Hi Dimitry,

    These drawings are auto-appended by a backend system. The person responsible for spec'ing the device (and datasheet) aren't involved in this process. 

    I talked with one of our experts on PCB design, he suggested that the vias are used or not used based on the max junction temperature supported by the device. (Meaning the backend system probably chooses a landing pad with Vias when TJ is large or potentially power dissipation is expected to be high).

    I've looked at a few TI app notes which recommend how to Vias be placed:

    "For thermally challenging applications, TI recommends that the thermal vias be placed on a pitch of approximately 1,0 mm. Per standard PCB manufacturing capabilities, 0,3 mm diameter drill holes are recommended as a starting point, but a smaller via offers less risk of solder volume loss. On applications where solder volume loss through the vias is of concern, plugging or tenting can be used to achieve a repeatable process."

    I understand that this question is in regard to a competitor device (34350) which does not use thermal vias. From what I can see, our thermal coefficients are pretty similar but our device supports much higher junction temperature and ambient operating temperature (85C vs 125C with max junction up to 170C). This would mean that our device should be able to use the same landing pad as the competitor device. 

    For thermal performance, if the copper layer that is connected to the thermal pad is broken up by a lot of signal traces or power plane keep out regions, then it is better to use thermal vias to help dissipate the heat to other copper planes. 

    Quote from our PCB expert:

    "Each via in the thermal pad is like a thermal resistor and just like electrical resistors in parallel, they work in parallel to more efficiently transfer heat from the package into the board.  Reducing the number of thermal vias simply increases the overall thermal resistance and reduces the amount of heat transferred. "

    App notes related to thermal vias on thermal pads:

    https://www.ti.com/lit/an/slua271c/slua271c.pdf?ts=1717095379231&ref_url=https%253A%252F%252Fe2e.ti.com%252F

    https://www.ti.com/lit/an/sloa120/sloa120.pdf?ts=1717095968537&ref_url=https%253A%252F%252Fwww.google.com%252F#:~:text=TI%20recommends%20placing%20thermal%20vias,inner%20or%20bottom%20copper%20layers

    -Bobby