DS90UB953A-Q1: Why is the FPD-Link III signal affected by smartphone signals, Wi-Fi signals?

In addition, if BISTEN pin is floating (without pull-up or pull-down), then what happens? 

Hi Satoshi-san,

Thanks for reaching out with this question.

We have done EMC testing in the past with results showing that we pass emissions tests in CISPR 25 as well as immunity tests in ISO11452. Included a test  report below detailing tests which have been completed on similar FPD-Link III ADAS devices.

1537.951_958_EMC_102255-5_Final.pdf

One additional clarification, on the UB960 which you mentioned there is not a BISTEN pin. The UB954 does have this pin however. Could you please confirm which deserializer you're using here?

Please let me know if you have any questions here.

Best,

Thomas

Hi Mr. Thomas,

Thank you for your reply, but my questions are not solved.

1. About magenta noise
Thank you for providing EMC report.
Are FPD-Link signals so sensitive that they are easily affected by even slight external radio waves?
Or is it that our circuit layout is poor, making it susceptible to radio wave effects?

Have you ever experienced magenta noise due to distorted output from the deserializer?
I would like to know if the magenta noise is caused by other signal lines rather than the FPD-Link, so please let me know any information you have.

2.BISTEN
You're right.
I am considering the UB954 as another possible deserializer, so I would like to know how to handle the BISTEN pin.

Hi Satoshi-san,

Would you be able to share the schematic & layout for your board? We can certainly take a look and provide feedback on areas which could be improved to improve EMC performance. From a protocol standpoint FPD-Link signals are not this sensitive to EMC. These products are designed to be used in automotive & industrial applications where EMI/EMC performance is critical. Do you have any information on the cable type you're using here?

For the UB954 BISTEN pin we have guidelines in the datasheet as to how to use:

If BISTEN is pulled down to GND we can always enable BIST via registers as shown in datasheet section 7.5.12.2 BIST Operation Through Register Control. It is not recommended to leave this pin floating.

Best,

Thomas

Hi Mr. Thomas,

I'm sorry, but it's difficult to send you the design data due to information management issues.
I will try to make it possible to send it to you.
As for the cable, I used 1.5DS-QEHB with FAKRA connector.

Thank you for information of  BISTEN.

Best Regards,
ANDO Satoshi

Hi Satoshi-san,

Thanks for the feedback. If you would like to continue layout discussion we can discuss over email or over private E2E message rather than public forum, I sent you a friendship request there.

Best,

Thomas

Hi Mr. Thomas,

Thank you for your suggestion.

I'm still in the process of submitting the design data, but comparing the register values ​​when the output image from the deserializer is distorted and when it is normal.
Is there anything I can say based on this information? At first glance, it seems like the FPD-Link video is distorted and cannot be converted to CSI.
Do you have any more specific advice?

And do you have any data of TDR?
I am performing a TDR measurement on my PCBA, and have found that the impedance around the IC drops.
If you have any TDR results for each SerDes, I would like to see them for reference.

Best Regards,
ANDO Satoshi

Hi Satoshi-san,

It looks like these registers are from the UB960, included notes below:

1. RX port status 1 indicates lock loss flag asserted with BCC CRC errors as well
2. RX port status 2 indicates FPD3 encoder error and buffer error
3. line length in error case is not present, has the camera stopped streaming here?
4. CSI RX status indicates errors though out

It seems that there are quite severe errors which are seen here, do you have background on the EMC stress which is applied here? We have worked with the ISO 11452-2 standard for immunity in the past.

Best,

Thomas

Hi Mr. Thomas,

>has the camera stopped streaming here?
Streaming continues, but the video output from the deserializer stops or becomes distorted.
The video returns to normal when the device emitting the radio waves causing this is moved away.

I'll check about  ISO 11452-2.
I would also be grateful if you could show me any TDR measurement results if you have any.

Best Regards,
ANDO Satoshi

Hi Mr. Thomas,

I just sent you the design data via private message. Please review it.

Also, in the recommended circuit, PDB, MODE, and IDX are all pulled up to 1.8V, and our circuit does the same,
but if that's the case, T4 in the power-up sequence is not satisfied and it becomes 0s.
Is this okay?

Best Regards,
ANDO Satoshi

Hi Satoshi-san,

Thank you, I can review this layout later next week. Could you please provide a capture of your power-up sequence? The mode and IDX voltages should both be stable before PDB. In this case T4 is the time for mode and IDX to be stable, allowing the device I2C address to be defined as well as the FPD RX mode. 

Best,

Thomas

Hi Mr. Thomas,

Thank you for your reply.

I attached the capture of power-up sequence; PDB, IDX, MODE and 1.8V(VDD18).
As you say, IDX and MODE stabilize before PDB.
Does this result seem OK?

Best Regards,
ANDO Satoshi

Hi Satoshi-san,

Let me check on this tomorrow for you.

Best,

Thomas

Hi Satoshi-san,

These screenshots look fine here, we're bringing IDX and mode up and stable before the PDB reaches VIH.

Best,

Thomas

Hi Mr. Thomas,

Thank you for checking the sequence.
I look forward to your continued support with design reviews.

Best Regards,
ANDO Satoshi

Hi Satoshi-san,

Will provide feedback on design tomorrow.

Best,

Thomas