DP83TC812R-Q1: Unable to communicate with processor

Hello,

You will find SNLA431 useful for this issue, specifically section 4.11. I see that link is up in register 0x1, so the issue is likely with the MAC interface. For RGMII interface, some skew must be introduced between clock and data. I see the PHY is set to align mode, is the MAC introducing shift on RX and TX? Can you please also share the schematic with me?

Thanks,

David

Hi,

  The schematic diagram of DP83TC81R refers to the official design TIDA-020047. Currently, RXD2 and LED-0 are connected to pull-up resistors and other open positions;

Hi,

Is the MAC introducing shift on RX and TX? Please share your schematic with me for review.

Thanks,

David

Hi David,

   The schematic is TIDA-020047, you can download it from the Ti website.

customer has updated the progress. The following figure shows the waveform of RXD0 RXCLK on the PHY side

Hi,

Can you please check with the processor team that skew is being introduced on the TX and RX RGMII lines. If this is not being done, we can introduce it on the PHY in register 0x602. You may try writing 0x0602 = 0x0003 and see if the issue resolves.

Please also let me know how you are determining "DP83TC812R-Q1 can not communicate with processor AM2732".

Thanks,

David

Hi,

Writing 0x602 was unsuccessful, the value remains at 2. Can you please check if there are any issues with the customer's writing.

The above waveform was sent by AM2732, and the PHY did not respond

some more information

The value read from the 602 register is 3, and there is an error when using LoopBack.

Hi,

Are you able to determine if data transfer is functional in one direction but not the other? Or is there an issue with both RX and TX? Please let me know how you are determining DP83TC812R-Q1 can not communicate with processor AM2732.

Can you please probe the RGMII TX_D3 signal alongside the TX_CLK signal, zoomed in so I can see the setup and hold times. And the same for RX_D3 and RX_CLK as well. 

Please also check with the AM27 team about this issue, to ensure that the correct RGMII configurations are applied to the MCU.

Thanks,

David