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DS90UB953A-Q1: DS90UB953A-Q1: [ti960][ti953] i2c scl signal measured shown 100Khz when Local slave proxy Ti960 I2C set fast plus mode (1Mhz), remote mast proxy ti953 i2c set fast plus mode(1Mhz)

Part Number: DS90UB953A-Q1

Tool/software:

In some cases, i2c scl signal measured shown 100Khz when Local slave proxy Ti960 I2C set fast plus mode (1Mhz),  remote mast proxy ti953 i2c set fast plus mode(1Mhz).

case 1. Just connect ti960 to host processor, i2c controller of host controller set i2c speed fast plus (1Mhz), i2c analyzer measured shown as expected, 1Mhz.

but when plugin ti953, i2c analyzer shown i2c SCL reduced to 100Khz, no matter ti953 I2c speed set standard/fast/fast-plus.

case2. For some deug reasons,  we read back ti953 register value just after set, and  RESET_CTL Register (Address 0x01) reset ti953, need 3ms delay for i2c access, so

a bug when we directly read back , i2c read failed.   And this behavior also casued i2c scl signal shown 100Khz, even we set Local slave proxy Ti960 I2C set fast plus mode (1Mhz),

 remote mast proxy ti953 i2c set fast plus mode(1Mhz).  (we checked ti953 register, scl high time, 0xb = 0x6, scl low time 0xc 0xb.)

e.g 1

Ti953 fast-plus , ti960 fast-plus, serdes i2c debug Disabled 

SCL 1Mhz

SCL clock stretch 14.125  us

 

e.g 2

Ti953 fast-plus , ti960 fast-plus, serdes i2c debug Enabled

SCL 100Khz

SCL clock stretch 18 us

 ...

 

  • e.g 2 i2c signal image:

  • Hello,

    Thank you for reaching out. Are you referring to the local I2C on the 960 or the 953? Note that after connecting the devices and performing a reset, it is expected for I2C functionality to not be available immediately as the devices must lock onto each other for communication. Register 0x0A of the 953 should also be set to 0x12.

  • Hi Merillat

    Thanks for quick respones!

    1. the i2c signaling image i'm referring to local i2c on the ti960, all set up as below:

    2. And yes, I understood i2c functionality do not available after reset ti953 for about 3~5ms. What i don't understand is why during this 

    locking time, i tried few time i2c access (failed for sure), but how does this impact i2c speed of local i2c on ti960 when ti960/ti953 finished locking?

    is there any logic could explained this? or it's a un-expected behvior so we just need avoid i2c access during this locking time slot?

    3.I'm tring to set register I2C_CONTROL2 0x0A to 0x12 (original value is 0x10) of ti953 during configuration,

    but it still reproduced issue describled as title.

    Besides, could you please explained why 0xA register of ti953 is the key register related to local i2c speed on ti960?

    (from this register description, i only see it related to

    a. i2c watch timer

    b. SDA setup time relative to rising edge of SCL during ACK cycle.)

  • During the locking time of the serializer and deserializer, there is essentially no connection between the two devices. This means that there can not be any communication going across the forward channel, and the deserializer behaves as if there is no serializer connection. In general it is recommended to temporarily delay I2C during this time period as the devices are not able to behave as they would during normal operation.

    The 0x0A register needs to be set to 0x12 so that the I2C watchdog timer is sped up to 50 microseconds. If the timer is not sped up, the I2C bus will be held for at least 1 full second after a transaction is detected, preventing any I2C transactions from reaching other devices in the system. This register setting does not impact I2C speed, but it does impact the I2C functionality in multi-device systems. This is especially important during initialization scripts. 

  • thanks Merillat.

    this issue root caused that our i2c driver will reset speed mode when encountered access failed. So after ti953 reset_ctrl read back failed, it changed to i2c standard mode.

    Btw, we will measure i2c signal whether held ACK 1s or 50ms by i2c watchdog timer, thanks a lot.