TUSB8020B: PCIe REFCLK Connection

juan juan

Other Parts Discussed in Thread: TUSB8020B, TUSB7340

I went through the TUSB8020B IC datasheet and at page 25 (Figure 7-3. Reference Design 1), REFCLK pins are routed to a connector.

What i suppose here, the PCIe communication is based on separate clock architecture.

So why do you still make a REFCLK connection as both Root Compex and End Point would have a separate clock with a required ppm tolerance.

I'm puzzled as to why a REFCLK connection is still made.

It would be great if you can elaborate it

10 months ago

0 Brian Zhou 10 months ago

TI__Guru*** 138335 points

Hi Juan:

PCIe block in TUSB7340 need it's own reference clock to make it work, since PCIe slot on the PC will provide 100Mhz reference clock so that TUSB7340 can take advantage of it. let me know if you still hav question.

Best

Brian

0 juan juan 10 months ago in reply to Brian Zhou

Prodigy 20 points

Thank you for your quick reply.

I have few more questions in related:

1-In terms of PCIe standard, is this a common clock configuration or separate clock configuration?

2-Is it needed to make length matching between clock and data lanes?

+1 Brian Zhou 10 months ago in reply to juan juan

TI__Guru*** 138335 points

juan juan said:
1-In terms of PCIe standard, is this a common clock configuration or separate clock configuration?

It should be common clock since it shares reference clock with others.

juan juan said:
Is it needed to make length matching between clock and data lanes?

no need to matching trace lengths between clock and data lanes.

Best

Brian

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TUSB8020B: PCIe REFCLK Connection