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DS125DF1610: How to improve the CDR jitter?

Matthieu FOURNIER
Prodigy 20 points
Part Number: DS125DF1610

Tool/software:

Hello e2e Support,

In our applications, we link machines and, as result, up to 13 retimers in cascade.

As discuss with TI support team, cascading retimers results in jitter peaking.

Could a better quality 25MHz clock (REF_CLK_IN) (better stability and lower phase noise) improve the CDR jitter (or reduce the noise added by other retimer elements)?

Could a better quality (less noise) 2.5V power supply improve CDR jitter (or reduce noise added by other retimer elements)?

Best regards,

Matthieu

  • 0
    TI__Mastermind 23707 points

    Hi Matthieu,

    The REF_CLK_IN in this device is used to get the internal VCO to roughly the correct frequency for CDR lock, but is not actually used for clock generation for the CDR.  Because of this, we would not expect a better quality REF_CLK_IN to improve CDR jitter.

    A better quality 2.5V supply might help.  Your goal for this supply would be to reduce jitter within the CDR bandwidth.

    Are you able to share more details about why you're cascading up to 13 retimers?  This is not something we typically see.

    Thanks,

    Drew