Tool/software:
Design details:
- Application data rate - 5.6376 Gbps
- REF_CLK - 312.5MHz
- Manual Data Rate calculation
| VCO setting | ||||
| PARAMETER | VALUE/EQUATION | Gojira | COMMENT | Hex/Bin |
| Reference Clock | F0 | 312500000 | ||
| Desired VCO Frequency | F1 | 11,275,200,000 | To support sub rate of 5.6376 Gbps | |
| Number of Reference Clocks | N =1024 | 1024 | ||
| VCO Freq ÷ 32 | F2 = F1 ÷ 32 | 352,350,000 | ||
| Counts of VCO Freq ÷ 32 required | F3 = F2 x N÷F0 | 1154.58048 | ||
| Counts of VCO Freq ÷ 32 required rounded | F4 | 1155 | Round F3 to the nearest integer value. Convert this value to binary. Program the upper 8 bits to ch register 0x61(0x63) and the lower 8 bits to ch register 0x60(0x62). Be sure to set channel register 0x61(0x63)[7] to 1 to enable the override function for manual programming. | 483 |
| PPM error due to rounding | Err = 1e6 x (F4– F3) ÷ F3 | 363.3527565 | ||
| Required PPM tolerance | T | 1000 | ||
| VCO Freq ÷ 32 +PPM tolerance | F5 = (1+ T÷1e6) * F2 | 352702350 | ||
| Rounded Counts of the VCO Freq ÷ 32 +PPM tolerance required | F6 = F5 x N÷F0 | 1156 | ||
| PPM Counts delta | F7 = F6– F3 | 1.41952 | Convert this value to binary. Program the most significant bit channel register 0x67[7(6)] and the rest of the bits to channel register 0x64[7:4] | 1 |
4. Channel Register setting
| Channel Reg | Value | |
| 0x60 | 83 | Group 0 count LSB |
| 0x61 | 84 | Group 0 count MSB |
| 0x62 | 83 | Group 1 count LSB |
| 0x63 | 84 | Group 1 count MSB |
| 0x64 | ee | |
| 0x67 | 20 | |
| 0x2F | 06 | group divider 2,4 0x2F[7:4] =2'b00 |
Observation:
Ref CLK is OK by checking Register B.
reg 0xB --> 0x40
Register 78 shows that we can detect signal at RX, but, but CDR is not locked.
reg 0x78 --> 0x20
All other regester setting are using the default value.
