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DP83867IRPAP-EVM: DP83867ERGZ-R-EVM RGMII connection

Part Number: DP83867IRPAP-EVM
Other Parts Discussed in Thread: DP83867ERGZ-R-EVM, TLK106

Tool/software:

Hello,

I have designed a board that includes the Novatel OEM 7700 receiver (which has its own PHY). On the same board, I have added another PHY so that it can be connected via RGMII to an FPGA on a different board through a cable. Before I connect it, I want to perform a test to confirm that the design is correct. I have the devboard, specifically the DP83867ERGZ-R-EVM, and I have connected the RGMII pins. I connected the RXD0..3 pins from one board to the TXD0..3 pins on the devboard because all I need from the devboard is for it to pass the information so I can check with my PC to see if it works. The problem I’m facing is that it doesn't work at all, as if the information is not passing through the devboard. What can I do about this? Should I connect via JTAG? Do I need to set a specific mode on the devboard?

  • Hi Aris,

    Please confirm these connections are being made between each 867:

    CTRL and CLK connections are also required for data transmission.

    Are both DP83867's linked up in the same speed during the test? If so, the only EVM modification that might be required is to adjust straps for RGMII clock skew to meet timing requirements.

    If you are still facing issues after making these connections and confirming link, please share a scope-shot of RGMII clock and data on both the FPGA and EVM side.

    Thank you,

    Evan

  • Hello Evan, thank you very much for your response. The first test I want to run is to try out the board I have built (you can see it at this link: https://gitlab.com/librespacefoundation/phasma/phasma-gnss-electronics). I aim to pass the RGMII signals from the dev board through to my PC. The connections I’m using are shown in the block diagram I made for you.

    I suspect, as you mentioned, that I might need to make some adjustments on the dev board (adjust straps for RGMII clock skew as you also said) . This is probably what I'll try next. With the Novatel board, which has the TL106, I have successfully connected to my PC. However, the setup in the block diagram that I created to test the PHY on the same board (the DP83867) is not working when I try to connect it to my PC. I want to run this test first before connecting it to the other system (the FPGA) to ensure that the PHY(DP83867)  on the board works properly with the GPS Receiver(TLK106).

    Thank you again for your response.

  • Hi Aris,

    Thank you for sharing the board and block diagram references.
    I see no concerns with the schematic and connections.

    For debug, please help confirm:

    1) PHY link is up (register 0x1[2] = '1')

    2) If link is up, iterate RGMII delay settings to confirm if this is a timing issue:

    0x32[1:0] to enable/disable RGMII shift/align modes

    0x86[7:0] to tune the TX/RX CLK delays in shift mode. Testing in align mode and shift mode with various delays (1,2,3,4 ns) will help confirm timing issue as the root cause.

    If possible, sharing scope-shots of RGMII clock and data on PHY and MAC-side will help confirm if signaling is meeting receiver requirement.

    Thank you,

    Evan