I am using the SN75LVPE5412 IC in a PCIe Gen5 setup.
Current Configuration:
- Adjustment Method: Using PIN MODE.
- Configuration: EQ L5 / Flat Gain L4 (default).
Current Usage Situation:
I have two PCIe Gen5 slots implemented on a motherboard:
- Slot 1: Closer to the CPU (signal source).
- Slot 2: Farther from the CPU.
Both slots utilize the same CPU_TX15 lane:
- Scenario 1: When PCIe X16 Slot 1 requires X16, the signal path is CPU_TX15 > PCIe X16_TX15.
- Scenario 2: When PCIe X16 Slot 1 requires X8 and PCIe X8 Slot 2 requires X8, the signal path is CPU_TX15 > PCIe X8_TX15.
In summary, the signal switches between different paths depending on whether X8 or X16 is required.
Current Issue:
During PCIe Gen5 compliance testing in the lab:
- Slot 1 (closer to the CPU): Fail.
- Slot 2 (farther from the CPU): Pass.
Supporting Documentation:
I have test reports provided by the lab:
- One Fail report.
- One Pass report.
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PCIe 5.0 System Test Results
Pass/Fail Results
Overall: FAIL
Waveform: Gen5-P8.bin
Template Name: Optimize_CTLE
TX Preset: 8
Lane: 7
Mean UI: 31.30294ps
CTLE Index: 3
CTLE Gain: -7db
Adapted V_ref: 96.19141mV
DFE Tap 1: 29.78516mV
DFE Tap 2: -13.91602mV
DFE Tap 3: 4.15039mV
Target BER: 1E-12
Composite EW: 14.16294ps
EW @ BER: 8.99249ps
Composite EH: 126.25077mV
Eye Height @ BER: 65.43536mV
SSC Frequency: 31.6E3
SSC Depth:
Jitter:
Composite EW: 14.16294ps
EW @ BER: 8.99249ps
Extrapolated TJ: 22.31046ps
Deterministic Jitter: 10.39006ps
Random Jitter (RMS): 847.28000fs
Data-Dependent Jitter: 13.09392ns
Transition Eye:
Min Trans EH @ BER: 71.29001mV
Max Trans EH @ BER: 276.82888mV
Composite Trans EH: 147.60470mV
Mean Trans EH: 144.20626mV
Extrapolated Noise (H): 7.69226mV
Extrapolated Noise (L): 7.17916mV
Deterministic Noise (H): 28.49425mV
Deterministic Noise (L): 29.71075mV
Random Noise (H): 6.67142mV
Random Noise (L): 5.78542mV
Non-Transition Eye:
Min NT EH @ BER: 94.60017mV
Max NT EH @ BER: 309.72575mV
Composite NT EH: 173.26350mV
Mean NT EH: 171.10848mV
Extrapolated Noise (H): 13.03719 mV
Extrapolated Noise (L): 14.44539 mV
Deterministic Noise (H): 6.03272 mV
Deterministic Noise (L): 2.85984 mV
Random Noise (H): 2.84906 mV
Random Noise (L): 3.70048 mV
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PCIe 5.0 System Test Results
Pass/Fail Results
Overall: PASS
Waveform: Gen5-P8.bin
Template Name: Optimize_CTLE
TX Preset: 8
Lane: 7
Mean UI: 31.31427ps
CTLE Index: 2
CTLE Gain: -6db
Adapted V_ref: 87.89062mV
DFE Tap 1: 29.78516mV
DFE Tap 2: 4.15039mV
DFE Tap 3: 5.37109mV
Target BER: 1E-12
Composite EW: 18.81427ps
EW @ BER: 15.19100ps
Composite EH: 125.97510mV
Eye Height @ BER: 74.18331mV
SSC Frequency:
SSC Depth:
Jitter:
Composite EW: 18.81427ps
EW @ BER: 15.19100ps
Extrapolated TJ: 16.12328ps
Deterministic Jitter: 7.64821ps
Random Jitter (RMS): 602.39000fs
Data-Dependent Jitter: 76.12877ps
Transition Eye:
Min Trans EH @ BER: 67.42757mV
Max Trans EH @ BER: 250.69523mV
Composite Trans EH: 116.54255mV
Mean Trans EH: 130.35086mV
Extrapolated Noise (H): 7.26029mV
Extrapolated Noise (L): 8.49459mV
Deterministic Noise (H): 15.47785mV
Deterministic Noise (L): 16.34015mV
Random Noise (H): 6.67396mV
Random Noise (L): 6.69284mV
Non-Transition Eye:
Min NT EH @ BER: 90.86162mV
Max NT EH @ BER: 270.32807mV
Composite NT EH: 142.06527mV
Mean NT EH: 155.46957mV
Extrapolated Noise (H): 13.03719 mV
Extrapolated Noise (L): 14.44539 mV
Deterministic Noise (H): 6.03272 mV
Deterministic Noise (L): 2.85984 mV
Random Noise (H): 2.84906 mV
Random Noise (L): 3.70048 mV
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The above describes the current issue I am facing. Could you provide recommended EQ and Flat Gain settings for Slot 1, which is closer to the CPU but failing the PCIe Gen5 compliance test? I hope these adjustments can help the test pass. Thank you!
