DS25BR100: Interface forum

Peter

What is the required data rate? We have done some cable testing with some LVDS drivers/receivers, please see this app note, https://www.ti.com/lit/ab/slaa844/slaa844.pdf. 

Thanks

David

Dear David, thanks for coming back to me. Forgot to mention that SPI CLK will be around 33MHz.

As you probably noticed, my setup is different from the app note, as I have the communication fully isolated over two pulse transformers instead of a direct connection - which has a huge impact.

Thanks!

Peter

The app note I shared was done with CAT5E cable between LVDS with 5%, 10%, and 20% jitter. I understand your setup is different from the cable length measurement setup, but I do not know how to extrapolate the jitter performance across the transformers. I am wondering if we pick the 5% jitter margin, would that margin be sufficient to cover the setup difference?

Thanks

David 

I do not know.... which chip would you recommend for this setup?

Peter

We have verified SPI over LVDS using SN65LVDS31-33EVM, https://www.ti.com/tool/SN65LVDS31-33EVM in the past. Please see this link for the reference design, https://www.ti.com/lit/ug/tidued8/tidued8.pdf. The LVDS31-33EVM allows for data rates as high as 400 Mbps at short distances and for longer distances, like 50m, can also operate around 50 Mbps. So this will be my initial recommendation.

Thanks

David   

David, I had a rough 10m distance for LVDS in mind, but wasn't aware that 50m could be attained. However, this must be in perfect situations I presume - not like my setup where it is transmitted over two transformers... With the actual lvds chips, I reach 5m without a problem, 10m is too much (sometimes it works, mostly not). Are the chips you propose better ?

What is your thought about M-LVDS? It seems to be lower speed (what I do not mind as the max freq.is only 33MHz), and can achieve longer distances, which would be great in my setup. Any inconvenient compared to the SN65LVDS31-33EVM setup ?

Thanks!

Peter

What is the issue you are seeing with the 10m cable? Is it the signal degradation in terms of the amplitude or jitter? 

On the driver side, the M-LVDS drivers pose as drivers with a stronger drive (larger IOD). The stronger drive enables the M-LVDS drivers to drive signals across multipoint networks that are typically doubly terminated. Doubly terminated networks present a heavier load to the driver, so the stronger drive is necessary for retaining required signal amplitudes. 

On the receiver side, the input threshold levels differentiate the two types of M-LVDS receivers, Type 1 and Type 2. Type 1 receivers have threshold levels centered at 0V differential and provide higher noise margin than Type 2 receivers. Type 1 receivers are used in clock or data transmission applications that either require application specific external failsafe networks or don’t require failsafe provisions at all. Type 2 receivers have threshold levels shifted by +100 mV differential. The shift lowers noise margin but provides a known, low output state when a bus or a transmission line is undriven and having 0V differential bias.

Thanks

David

David, thanks for your reply.

I haven't taken the time to setup a measurement with two passives probes (do not have a differential probe unfortunately) to see if it's the skew or the amplitude that causes problems. What would you propose in either case to improve the signal?

Indeed, I read these things also in the documentation online. In my case (driver->transformer -> cable -> transformer->receiver) is this going to cause a problem somehow if I would use M-LVDS? There is no receiver connected to the driver (transformer for isolation), so I suppose I need to connect a load at the output of the driver. As it is connected to a transformer, I suppose I should apply an AC termination to couple it to the transformer like in the picture below - or do you have any other recommendation? For the receiver side, it's going to be the opposite (transformer, AC coupling, Voltage divider to 1.2V, receiver) - any remark/suggestion on this side?

As the type 2 receivers provide a low output state at idle, this causes a problem for Chip Select (which is active low) - so I must use a type 1. Do you have some info on external failsafe networks ?

Thanks for your precious time and info.

Peter

M-LVDS Type-1 receiver is similar to LVDS, include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type 2 receivers include internal fail safe, and have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference. So for Type-1 receiver, you could implement an external biasing as shown below. Please note inactive devices and receivers are prohibited from employing simple failsafe pullup circuitry that can charge the line to more than 2.4 V or less than 0 V and result in operation outside the minimum common-mode operating voltages.

If you are trying to AC coupling between the LVDS and the transformer, then the data needs to be DC-balanced which I do not believe will work with the SPI interface. 

Thanks

David

David, what would you propose to do in the case of an amplitude problem? How about a skew problem? Concerning the voltage divider implemented in the picture above, which resistor values do you recommend?

Thanks,

Peter

Do I understand well that R1 is connected between 3V3 and the upper signal, R2 connected between the upper and lower signal, and R3 between the lower line and GND ?

Peter

The amount of failsafe biasing depends on your application design parameter. With applications in low noise environments, you may want to choose to use a very small bias. For applications with less balanced interconnects and/or in high noise environments, you may want to boost failsafe. You also need to consider the common mode voltage that gets biased by the external resistors during the un-driven state. This is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and un-driven states, the common-mode modulation on the bus is held to a minimum. The external low value (a few kΩ typical) resistors R1 and R3 provide a low impedance path from the line to power/ground. This has multiple benefits: it provides a common-mode return path, it provides a shunt path for ESD and EOS events making the already rugged parts even more robust, and it also makes coupled noise lower in magnitude.

For example, if a 25 mV failsafe bias point is required (Vfsb), first determine the amount of bias current. 25 mV/100Ω is 250 µA. The bias current should be a least an order of magnitude smaller than the 3 mA loop current. Next determine the total resistance from the bias supply to ground −> 3.3V/250 µA = 13 kΩ. Since RT is 100Ω it can be ignored. Next determine the ratio of R3 to R1. This is 1.25V/3.3V = 0.378. Next calculate R3 as 0.378 of 13 kΩ and round down to a standard value (4.99 kΩ). R1 is equal to 13 kΩ − R3 = 8 kΩ. This network will provide a bias of +25 mV to the receiver.

For amplitude and skew problem, you want to minimize the amount of insertion loss, both the inter-pair and intra-pair skew from the PCB design and the CAT5 cable as much as possible. But in typical SPI communication, the SPI master sends data at rising edge and receives data on the falling edge within the same clock cycle. So the total round trip propagation delay must be less than half the SCLK period to avoid missing bits. I wonder if the issue you are having with longer than 5m cable is the latency of the clock itself. You may want to take a look at section 2.3 in the tidued8.pdf app note I sent and see if you can eliminate this round-trip delay.

Thanks

David