SN65DSI83-Q1: PLL LOCK with reference clock.

Devathi

Can you please share your schematic and video panel spec? If you enable the DSI83-Q1 internal test pattern, are you able to see the test pattern on the video panel?

Thanks

David

Hi David,

Can you please provide email id or accept the friend request. So that I can share to requested details.

Thanks and Regards,

Devathi Mahesh.

Devathi

I accepted your friendship request, please send me the details in a private e2e message.

Thanks

David

Hi David,

I have shared data sheet of display panel and Schematics.

And  By enabling DSI83-Q1 internal test pattern , Display is completely blank.

What might be the reason for getting blank? 

Note:

The generated frequency from the reference clock(CDCEL913) is 62.58 MHz.

Thanks and Regards,

Devathi Mahesh.

Devathi 

Are you using the DSI Tuner to generate the DSI83-Q1 register programming value? Please see attached DSI Tuner SW.

5315.DSI-Tuner.zip

Please see this link on how to use the DSI Tuner SW, https://www.ti.com/video/5829462797001. 

When I am comparing against your programmed register value against the video panel typical value, I see for example the VSYNC Pulse Width is not meeting the typical value. 

Attached is the DSI83 register programming value I generated for using REFCLK and enable the test pattern, can you see if it works on your side? Also what is the DSI CLK frequency you are using right now?

//=====================================================================
// Filename   : CSR_DavidLiu_REFCLK_Colorbar.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x04
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x25
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x03
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x16
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x03
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x15
0x35              0x00
0x36              0x03
0x37              0x00
0x38              0x15
0x39              0x00
0x3A              0x02
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

Thanks

David

Hi David,

1. Yes, We are using DSI Tuner to generate.

2. With CSR values of that you have shared , Display is still in blank no Test pattern is observed.

3.PLL is still unlock.

4.DSI clock frequency is 200 - 205 MHz .  mostly ~ 203.8MHz

i2c dump with CSR values that you have shared is

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 04 00 00 01 00 00    58ISD   ?.?..?..
10: 26 00 25 00 00 00 00 00 78 00 03 00 00 00 00 00    &.%.....x.?.....
20: 00 05 00 00 00 03 00 00 20 00 00 00 16 00 00 00    .?...?.. ...?...
30: 03 00 00 00 15 00 03 00 15 00 02 00 10 00 00 00    ?...?.?.?.?.?...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00    .....?..........
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00    ....@..?........

Please Let us know what frequency of reference clock we are suppose to use?

and also why PLL is not lock ?

Thanks and Regards,

Devathi Mahesh.

Devathi

To calculate the DSI_CLK, 

With LVDSCLK = 62.58MHz, bpp = 24, the DSI_CLK should be = 187.74MHz. 

Can you please verify that you are following the initialization sequence listed in the datasheet? This sequence is critical for correct operation of these devices. You want to make sure the REFCLK is up and stable before the DSI83-Q1 is out of reset. 

With the REF_CLK being 62.58MHz, you set the REFCLK_MULTIPLIER to 0x00 so the LVDS_CLK = REF_CLK. If you probe the LVDS_CLK, are you seeing the correct frequency?

Thanks

David

Hi David,

Test pattern of the display able to see .It is working fine,  there is some noicy in LVDC signal , that is now resolved. 

But when we disable the test pattern , Display is still in blank. What might be causing the issue?

Can you also give us the CSR values for the working build (Without test pattern).

Below is the i2cdump with test pattern enable,

    0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 84 00 00 01 00 00    58ISD   ?.?..?..
10: 26 00 25 00 00 00 00 00 78 00 03 00 00 00 00 00    &.%.....x.?.....
20: 00 05 00 00 00 03 00 00 20 00 00 00 16 00 00 00    .?...?.. ...?...
30: 03 00 00 00 15 00 03 00 15 00 02 00 10 00 00 00    ?...?.?.?.?.?...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00    .....?..........
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00    ....@..?........

Thanks and Regards,

Devathi Mahesh.

Devathi

Please see below for the register programming values without test pattern.

// (C) Copyright 2013 by Texas Instruments Incorporated.
// All rights reserved.
//
//=====================================================================
0x09 0x00
0x0A 0x04
0x0B 0x00
0x0D 0x00
0x10 0x26
0x11 0x00
0x12 0x25
0x13 0x00
0x18 0x78
0x19 0x00
0x1A 0x03
0x1B 0x00
0x20 0x00
0x21 0x05
0x22 0x00
0x23 0x00
0x24 0x00
0x25 0x00
0x26 0x00
0x27 0x00
0x28 0x20
0x29 0x00
0x2A 0x00
0x2B 0x00
0x2C 0x16
0x2D 0x00
0x2E 0x00
0x2F 0x00
0x30 0x03
0x31 0x00
0x32 0x00
0x33 0x00
0x34 0x15
0x35 0x00
0x36 0x00
0x37 0x00
0x38 0x00
0x39 0x00
0x3A 0x00
0x3B 0x00
0x3C 0x00
0x3D 0x00
0x3E 0x00

The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

Please make sure the line time (time from HSYNC to HSYNC) on the DSI input matches the line time on the LVDS output. The line time on the LVDS output is the total amount of horizontal pixels divided by the LVDS clock frequency. You can measure the line time on the DSI input with an oscilloscope by zooming in on the data stream on of the data lanes like below:

Thanks

David

Hi David,

The Line Time measured on the DSI side comes out as 19.86 us.  And we are almost matched line time by changing reference clk frequency to 67.86 MHz.

Good news is Display is working with reference clk, but we are getting display blank in some random cases(PLL unlock is happening during display is getting blank).

Can you help us in getting the acceptable difference in line time?

These are the i2cdump values when display blank taken place.

Our aim is to not to get display blank, But still even with the reference clk display blank is happening. Can you suggest us what are further steps need to take place to not get Display blank with the reference clk?

Thanks and Regards.
Devathi Mahesh

Devathi 

The line time has to match between the DSI input and the LVDS output, you can not have a difference in line time. 

Are you seeing the line time difference when you are getting the display blank? Any difference in power up sequence between the working and not working case? For example, is the clock stable in working case when DSI83 comes out of the reset? 

Thanks

David

Hi David,

Our team is working on required information. We will provide the information once it is done.

And  PLL unlock is happening randomly. There is no specific way to reproduce the blank screen.Can you brief what are the reasons to cause of PLL unlock ? 

Thanks and Regards,

Devathi Mahesh.