SN65DSI83-Q1: Does the 0XE5 error register can mapping to host directly or the error can mapping to INT pin

Hi,

You can set the IRQ_EN bit in register 0xE0 as shown below and also enable interrupt generation in register 0xE1.

The IRQ pin output is driven high when a bit is set in registers 0xE5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition.

Thanks

David

hello David:

thank for your quick reply ; so this need host(SOC) polling to read the 0xE5 value ,when error happened , then write 0xE1 register to trigger the IRQ event ? 

this behavior will occupy soc source ,we wander if can report the error automatic 

Hi,

The IRQ pin needs to be connected to the SoC first. 

You will then write to register 0xE0 and 0xE1 to enable error reporting through the IRQ pin. You can choose to report a specific or all DSI errors using register 0xE1. 

When a specific DSI error has happened, the IRQ pin will go high and then SOC will read register 0xE5 to understand the specific reported DSI error. The SoC can take the appropriate action to resolve the error and write a 1 to the corresponding error bit to clear it.

Thanks

David 

Hi David:

thank you , understood; 

other a question is regarding as PLL_UNLOCK bit ,value 1 means PLL lock status and is a normal status , right ? at my test bench , when the system works normally , i read the 0xE5 is 01 , this means no error ,right ?