DS90UH947-Q1: DS90UH947-Q1 & DS90UH948-Q1

Hi GH, 

Thanks for reaching out. Be default, the 94x SerDes have adaptive equalization which will gain the signal to adequate levels. When maintaining the system/PCB insertion loss/return loss guidelines, we would expect up to almost 15m of cable typically; so 5m seems shorter than expected. 

How many inches of FPD trace are on PCB?

What cable type is being used?

What PCLK is being used? 

With 1m cable, can you run the margin analysis tool?

Regards, 

Logan

Dear, Logan

Thank you for your reply.
The length of FPD trace of the SET PCB is 35mm (Con<->947),
and the length of FPD trace of the Monitor PCB is 60mm (Con<->948).
The cable type used Rosenberger cable (figure below) and is configured as STP connection.
We are using 85MHz PCLK
margin analysis tool cannot be run.

We would like to know if there is any amp or pre-amp IC applicable to FPD LINK III.

Additionally, We are currently using 100nF AC Coupling Capacitor. Please check if this will affect the above phenomenon.

Thank you, for your support.
Best regards,
GH Park

Hi GH, 

Thanks for the follow-up details. There is no amp other than the Equalization mentioned before. 

Do you have return loss/ insertion loss data at a PCB and/or total channel level? 

Do you mind also sending over the schematics? (I sent a Friend request so that it can be shared via private chat).

Regards, 

Logan

Dear, Logan

We can't measure return loss/insertion loss data.
We sent the circuit diagram through private chat.

Thank you, for your support.
Best regards,
GH Park

Dear, Logan

Dear, Logan

After "accept", it appears as shown below.
Please check where the circuit diagram should be inserted.

Thank you, for your support.
Best regards,
GH Park

Hi GH, 

Can you start a private chat with me and upload the files? 

Thanks, 

Logan

Dear, Logan

How do I use private chat?

Best regards,

GH Park

Hi GH, 

If you click on my Name, you will see an option to send a Friend request. Once that is down, you will see an option for direct private message. 
If that doesn’t work, I’ll provide TI drive link and access  code to upload to.

Regards,

Logan

Dear, Logan

I'm trying to send a pdf file, but getting an error like the one below.

Check again.

Best regards,

GH Park

Hi GH, 

I was able to finally get a message to go through via Private Chat. Please see if now you can upload the files to that chat thread, otherwise I also added a TI Drive folder which you can upload to. 

Regards, 

Logan

Dear, Logan

We sent you schematic via private chat 2 days ago.
Please check the schematic.

Thank you, for your support.

Best regards,

GH Park

Hi GH, 

Please find feedback attached below. From high level,  I see a back to back 948 and 947, just to confirm, is the input to 947 from SoC rather than the output of 948?

Regards, 

Logan

Dear, Logan

As shown in the block diagram of schematic, LVDS Switching is used at U24 & U25.
CASE 1. When using CAR AVN : Connect from LVDS output of 948 to input of 947.
CASE 2. When using ANDRIOD SET(SOC Output) : Connect from LVDS output of ANDROID to input of 947.

Black screen, touch don't work, etc is well shown in CASE1.

Thank you, for your support.
Best regards,
GH Park

Hi GH, 

Thanks for the explanation. The likely cause for the performance issues with case 1 is due to input jitter violation at the input of the 947. The input CLK jitter tolerance is somewhat tight for these devices due to the FPD-Link CLK being directly multiplied from the incoming PCLK. 

Can you measure the input CLK jitter of the 947? You can refer to the following guide: 

1780.947 Jitter and Skew Measurements.xlsx

Regards, 

Logan

Dear Logan

Sorry for the late reply.

We can't measure the CLK jitter you mentioned.

If it's due to CLK jitter, is there anything we need to add to the circuit?

We can do it if you mention addition of the circuit.

And we can test on vehicle.

Please check if there are any suspicious values, circuit, etc. in the schematic.

Thank you, for your support.

Best regards,

GH Park

Hi GH, 

Can jitter/skew be measured on the bench with oscilloscope? This is a device specification, and poor results are probable when in violation. So to confirm root cause, this data is encourage.

Can you also try PatGen with AON clock? 

Lastly - just to confirm my understanding, Case 2 above does not show the issue even with longer cable?

Regards, 

Logan

Dear, Logan

We have attached the waveform of CLK measured with the oscilloscope we have.(947 pin58)
We tried several ways to check, but we can't measure CLK jitter with the oscilloscope we have.
Also, we don't have the pattern generator you mentioned.
CASE 2 have an issue that occurs, but less frequently than CASE 1.

Thank you, for your support.
Best regards,
GH Park

Hi GH, 

If you use internal CLK and pattern generation on the second 947-948 link, do you get valid lock and stable video? 

Regards, 

Logan

Dear, Logan

We install it on the vehicle with the BLOCK configuration we provided.
The symptom does not appear on all vehicles, but only on some vehicles.(about 5%)
It is a symptom that appears when the cable length is long.
The symptom disappears when the cable length is applied to 50cm ~ 1m.(first, second 947-948 connecting cables)
Therefore, I think the second 947-948 link is stable video.

Thank you, for your support.
Best regards,
GH Park

Dear, Logan

Are there any updates?

Thank you, for your support.
Best regards,
GH Park

Hi GH, 

As mentioned above, this looks like a link margin/link robustness issue. In order to further comment on root cause, we would ask to provide the following data: 

• Jitter output of first 948 following the above guide to verify skew/jitter datasheet requirements
• Channel specification for both links
  • If long cable impacts issue, this could be an SI issue
• Confirmation of lock status of first 947-948, does the second link drop as a result of the first (especially in case 1)?
• If PCLK is lowered, does reproduction decrease?

Regards, 

Logan