DS90UH981-Q1: How to calculate I2C register read and write timing for FPD-Link IV TX→RX communication?

Tool/software:

Hi TI

I am working on an automotive display system using FPD-Link IV SERDES (e.g., DS90UB988-Q1)

I need to calculate the precise timing for I2C register read and write operations between the TX and RX.

I understand the calculation method, taking a slave device, a register as an example, the time it takes for I2C to read and write

Write:  start(1bit)+device add(7bit)+write(1bit)+ACK(1bit)+reg add(8bit)+ACK(1bit)+data(8bit)+ACK(1bit)+stop(1bit)

=29bit

Read:  start(1bit)+device add(7bit)+write(1bit)+ACK(1bit)+reg add(8bit)+ACK(1bit)+start(1bit)+device add(7bit)+read(1bit)+ACK(1bit)+data(8bit)+NACK(1bit)+stop(1bit)

=39bit

Time_I2C_write=29bit*(1/400kHz)

Time_I2C_read=39bit*(1/400kHz)

However, the calculation method of I2C communication time for the forward and back channels of FDP-LINK is not clear.

Could you clarify the following:

1. The bandwidth of the forward channel that actually transmits I2C.

2. The bandwidth of the back channel that actually transmits I2C.

3. Forward channel data packet format

4. Back channel data packet format

‌Use Case Example：

I‌2C_CLK: 400kHz

Forward Channel Line Rate:3.375 Gbps

Back Channel Rate:168.75 Mbps