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SN75LVPE5412: layout question

Part Number: SN75LVPE5412

Tool/software:

Hi,
For TI_SN75LVPE5412RUAR and TI_SN75LVPE5421RUAR:
The reference layer on the second layer (adjacent reference layer) beneath the IC for high-speed signals should be voided to maintain impedance.
Is there a defined specification for the dimensions of this voiding?
Thanks!
Jeff
  • Hi Jeff,

    For voiding under the high-speed pins we don't have specific guidelines, it is something that customers can do sometimes but not common enough to be part of our normal recommendations. I would say that for this kind of void, it is probably better to make the keepout exactly large enough to box the high-speed pins, and try to avoid making them wider than that. The reason is that we want to avoid making a large disruption in the ground plane through wide voids close to each other. In your picture the voids are larger than I have seen on past projects so it may be helpful to shrink them slightly.

    Best,

    Evan Su