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TPD5S116: Incorrect sys side SDA voltage when level-shifted from port side

Yangqi Guo
Prodigy 10 points
Part Number: TPD5S116
Other Parts Discussed in Thread: ESD224,

Tool/software:

Hi, I'm using two ESD224 + one TPD5S116 in my design which connects the SOC (sys side) and HDMI Type A connector (port side). The schematic screenshot is shown below:

While HDMI monitor can correctly display the content, we found out that the DDC I2C SDA waveform is abnormal when the signal is transmitted from slave (port) to master (sys), as shown below:

1. DDC port side, Ch1 = SDA, Ch2 = SCL

2. DDC sys side, Ch2 = SDA, Ch3 = SCL

From the waveforms, it is quite clear that sys-to-port translation is OK (from SCL waveform) for both logic high and low; the port-to-sys translation is OK for logic high, but for logic low, there is a positive offset voltage on port side of about 0.4V (which is still below the datasheet max VIH port spec of 0.3x5=1.5V, as shown below), yet the level-shifted SDA logic low becomes around 1.25V instead of expected 0V.

What could be the root cause here? Is there any issue regarding schematic connections? BTW, I have provided the external pull-up of 2.2k to SDA and SCL as well (R134 & R135 shown below, VCCIO6 = VCCA), which should form effective pull-up of 1.53k with 5k internal pull-up resistor in TPD5S116. Could this be the issue?

  • 0
    Prodigy 10 points

    To follow up, I have tried removing external 2.2k pull-up, but the waveform stopped getting generated on the sys side following the same HDMI console command. I then tried to replace 2.2k with 220k pull-up (100 times) and got the following waveform after the console command:

    It can be seen that the translated logic low is now about 0.5V instead of previous 1.25V. Given that the SOC spec for max VIL is 0.8V, it is now meeting the system specs. This implies that Rdson of the TPD5S116 is pretty high at about 1k, in order to form a voltage divider with 1.53k effective pull-up resistance. Is 1k Rdson expected by TI?

    Moreover, could you explain the exact functionality of 300mV voltage source, as I'm not sure if I understand correctly from datasheet? What I can think of is that when port B toggles from high to low, the A-side MOSFET turns on, and the 300mV voltage source lifts up port A by 300mV which ensures CMP1 output is low, thus the B-side MOSFET will not turn on. However, if port A toggles from high to low, CMP1 will give output high, which turns on MOSFETs at both A and B sides. What exactly is the point of making such a configuration? While the disadvantage is clear (when level shifting logic low from B-side to A-side, the A-side output will have some positive offset voltage of about 500mV), the advantage is not clear to me.

  • 0 in reply to Yangqi Guo
    TI__Genius 9540 points

    Hi Yangqi,

    To be honest, this is an older part and much of the development team has changed since it was released.  So I don't have a ton of background on this device.

    I don't believe a 1k RDSON is expected.

    One item I need clarified is your I2C pullups.  TPD5S116 has internal I2C pullups, so I don't expect any are needed in your schematic.  For example, it appears R134/135 are in parallel with R_PUA (5k).

    Yangqi Guo said:
    I have tried removing external 2.2k pull-up, but the waveform stopped getting generated on the sys side

    Is there any other potential issue at play here?  I expect I2C should work via internal R_PUA.

    Regards,
    Eric

  • 0 in reply to Eric Hartigan
    Prodigy 10 points

    Hi Eric,

    Yes, the 2.2k external pull-up resistor connects to the same supply as TPD5S116, which means the effective pull-up resistance, Ru = 5k // 2.2k = 1.53k, as mentioned previously.

    Eric Hartigan said:
    I don't believe a 1k RDSON is expected.

    But it looks like that is what's happening: when MOSFET is turned on, effective voltage to be divided = VCCA - 300mV = 3V, by Rdson and Ru.

    Case 1 (2.2k external pull-up): Ru = 5k // 2.2k = 1.53k, VSDA = 1.25V from waveform, -> Rdson ~ 1.1k.

    Case 2 (220k external pull-up): Ru = 5k // 220k = 4.89k, VSDA = 0.55V from waveform, -> Rdson ~ 1.1k again.

    This means the assumption that Rdson = 1.1k is likely true. Please help to check if this is indeed unexpected; if so, what is the expected Rdson?

    Regarding the issue that removing external pull-up resistor resulting in no waveform, I can see 3.3V high for both SDA and SCL on the sys side, so TPD5S116 internal pull up is working. I will check with SOC vendor for this issue.

  • 0 in reply to Yangqi Guo
    TI__Genius 9540 points

    Hi Yangqi,

    Understood on your calculations.  I think the key here is that we need to limit the pullup resistance to reduce the sink current during VOL state.

    Based on the datasheet, you should see a maximum of 0.17*VCCA on the system side, so ~561mV.  This aligns with what you measured with 220k (5k internal pullup dominates).

    On the connector side, you should see VOL maximum of 0.4V assuming no external pullups.

    I suggest continuing without the external pullups and seeing if the issue persists.

    Regards,
    Eric

  • 0 in reply to Eric Hartigan
    Prodigy 10 points

    Hi Eric,

    Got it, the VOL issue on the sys side is clear to me now.

    Could you please also help me to understand the point of 300mV voltage source on the sys side MOSFET?

    Yangqi Guo said:

    Moreover, could you explain the exact functionality of 300mV voltage source, as I'm not sure if I understand correctly from datasheet? What I can think of is that when port B toggles from high to low, the A-side MOSFET turns on, and the 300mV voltage source lifts up port A by 300mV which ensures CMP1 output is low, thus the B-side MOSFET will not turn on. However, if port A toggles from high to low, CMP1 will give output high, which turns on MOSFETs at both A and B sides. What exactly is the point of making such a configuration? While the disadvantage is clear (when level shifting logic low from B-side to A-side, the A-side output will have some positive offset voltage of about 500mV), the advantage is not clear to me.

  • +1 in reply to Yangqi Guo
    TI__Genius 9540 points

    Hi Yangqi,

    I agree with your understanding.  It is necessary to avoid getting stuck in the low state once an input low is received.

    Example 1, Port A toggles HIGH-LOW-HIGH:

    • HIGH: CMP1 outputs LOW.  No FETs are enabled
    • LOW: CMP1 outputs HIGH.  B side FET enabled.   A side FET gets enabled as a result.  CMP1 continues to see output HIGH so long as the Port A signal is externally driven <150mV.
    • HIGH: CMP1 sees 300mV while A FET is still enabled.  CMP1 output changes to LOW, B FET disables, A FET disables as a result

    Example 2, Port B toggles HIGH-LOW-HIGH:

    • HIGH: A FET remains off, CMP1 outputs low, so B FET remains off
    • LOW: A FET is enabled.  CMP1 still outputs low since 300mV>150mV, B FET remains off
    • HIGH: A FET is disabled, CMP1 outputs low, B FET remains off.

    If the 300mV source weren't present when a logic LOW is received, both FETs get latched ON, forcing the pin to be stuck in the LOW state.

    Regards,
    Eric

  • 0 in reply to Eric Hartigan
    Prodigy 10 points

    It's very clear to me now, thanks for your explanation!