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Original question:

DP83822H: DP83822

DP83822I: No TX CLK or RX CLK out but I see a 25 MHz clock coming into XI

Blake Beard
Prodigy 20 points
Part Number: DP83822I

Tool/software:

Hello, 

I am having trouble getting my DP83822IRHBT to work with an FPGA.  It turns on, draws current, is not in RESET or PWDN, I've checked the strapping pins multiple times.  I did remove the LED series resistor pins because I didn't have pull-up and pull-down resistors in initially.  I'm not sure why I'm getting a flat 0V out of the TX CLK and RX CLK.  Any thoughts? 

Thank you, 

Blake 

  • 0
    TI__Guru**** 177151 points

    Hi,

    This could be a symptom of failed strap setting, link failure, or MPU is not enabling correct MAC interface.

    Please confirm:

    • Register read value of 0x17 (to confirm which mode is enabled)
    • Register read value of 0x467 and 0x468 (to confirm the strap setting). Please note these are extended registers
    • Register value of 0x1 (to confirm link up)

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Apologies for not getting back to you.  We were unable to look at any register values because they were always high.  The FPGA connected to the PHY was pulling multiple strapping pins high, putting it in an unknown state.  Once we figured that out, it fixed it.  Thank you for your time.