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TLIN1431-Q1: Queries on Watchdog and nRST

Sri Viswa Sathiamoorthy
Prodigy 225 points

Part Number: TLIN1431-Q1

Tool/software:

Hi,

1)What is the difference in nRST function when using the TLIN1431-Q1 in SPI mode vs Pin control mode? In the datasheet, it is specified as defaulted function in SPI mode.

2)Whether the below listed values in the below table for SPI is total window time? For example, if we choose WD_TIMER as 000 and WD_PRE as 11, then chosen total window

time is 16ms?

3)Then whether watchdog has to be serviced with 5.6ms to 10.4ms for 16ms window selection?

Calculation:

4)What is the time duration between watchdog error and reset trigger time for SPI control mode? (I assume it depends on counter but considering it as a permanent fault - any number is available)

5)In pin control mode, it is mentioned that WDT sets upper boundary of the window watchdog. Whether the values listed , eg for GND - 32ms to 48ms is total window size?

6)What is meant by Current mode?

Thanks,

Sri Viswa

  • 0
    TI__Guru 67117 points

    Hi Sri,

    1. Pin control uses the pin level state diagram figure 8-16 while SPI mode uses figure 8-17. The tNRST_TOG spec is also different, and faster for SPI mode and can be programmed as needed using the registers. In SPI mode there is more flexibility where more fault / interrupts reporting can be done I.e., faults that forces nRST low in pin mode can be reported as interrupts instead and failsafe / watchdog behavior can be disabled unlike pin mode where it is always enabled.

    2. Yes.

    3. No, please see 8.3.22.10.7 of the data sheet as the 8.8 ms after the window starts and the latest safe time as 14.4 ms.

    4. This is programmable dependent on the chosen window length (the 16 ms for example) and the watchdog error counter programmed. I.e., Number of error counts programmed * the configured total window length ± the 10 % oscillator. For example, 1 incorrect trigger will cause the transition where a default tMSRST_TOG in SPI is 2 ms with a 16 ms window and counter = 1. Hence, the trigger will lead to a restart withing that window (16 ms ± 10 %) and nRST low for the configured tNRST_TOG.

    5. Yes

    6. This is the internal device state where the device enters when handling protection events, for fault recovery and not user configurable, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 225 points

    Hi Michael,

    Thank you.

    I have further doubt in HSSC pin in SPI control mode. As per the datasheet, we can use FSO pin as HSSC pin when we configure HSS as HSSC controlled i.e we can toggle ON/OFF the HSS when we provide high & low signal to HSSC pin even in SPI mode using the above configuration.

    Whether my understanding is correct?

    Thanks,
    Sri Viswa

  • 0 in reply to Sri Viswa Sathiamoorthy
    TI__Guru 67117 points

    Hi Sri,

    Yes, your understanding is correct, thanks.

    Best Regards,

    Michael.