Part Number: DP83825I
Other Parts Discussed in Thread: DP83825EVM
Dear TI team,
I am looking for some guidance or debugging tips with an issue we are having bringing up the DP83825I ETH PHY module.
Our current situation is that the DP83825I is unable to establish a link using 100Mbps speed. It can establish a link at 10Mbps with several link partners (any commercial Ethernet device we tried) or with another instance of our own design.
I will try to disclose all relevant information as we see fit. Please feel free to ask for more information if things are unclear.
Current behaviour
- Using the default power up configuration (AN on, 100Mbps full duplex capability advertised) - the PHY is not able to reach a "link established" state - i.e. bits 2 and 5 in the BMSR register (0x1) are never asserted. Seems like AN never completes using this configuration. This is consistent with every link partner we tried.
- When setting the advertised speed to 10Mbps by writing 0x61 to reg 0x4 on either side of the link, the link is properly established both when using AN and when forcing the speed without using AN.
- Disabling AN and trying to force a 100Mbps link doesn't establish a link.
- Using half duplex 100Mbps advertised for AN, or when disabling AN and trying to force it also doesn't yield a valid link.
Debug steps taken and findings
- All loopback modes are able to establish a link in both 10Mbps and 100Mbps full duplex modes - i.e., asserted bits 2,5 in the BMSR register.
- When using a loopbacked Ethernet cable (i.e., wires 1-3 and 2-6 soldered and a cable of length ~10CM), the "link established" indication is correctly asserted with 100Mbps speed in full duplex. i.e device can pass AN and establish a link with itself using any electrical design we tried (described below).
- BIST test using PRBS packet generation passes without errors using analog loopback - i.e., reg 0x16 is showing PRBS active and locked, no errors counted in reg 0x18.
- When connecting two identical DP83825I PHY designes (any of the designs 1-5 described below) we can validate both PHYs correctly latch the link partner's capabilities in their corresponding ALNPAR register (reg 0x5 bits 5:8). Our conclusion from this is that the capabilities are advertized and decoded correctly by both sides but the link establishment fails afterwards indicating the AN did not complete in the BMSR register at address 0x1 bit 5.
Electrical Design information and steps taken
Verified voltage levels, resistors, and tolerance values for peripheral devices with respect to the advertised specifications.
The reference clock is 25MHz provided by an external CMOS level oscillator in RMII master mode.
We have tried 5 different electrical designs using different connection types between the RJ-45 connector and the PHY itself (attached and marked as ETH1-5 in the attached PDF):
- Full setup using Magnetics and chokes as indicated by the reference design we have, to the best of our understanding.
- Same as 1, without the choke device.
- Choke only connection.
- Using 100nF caps
- Using 33nF caps
All described designs display the exact same behaviour.
Our Design Documentation:
2025-10-13 PHY_Test_RJ45_v1 - Schematics (Rev.3).PDF
We also tried disabling Auto MDIX and forcing swaps (bit 5 in CR3 reg 0xB) without success.
Tried robust auto MDIX modes without success.
VOD levels - tried 50/150% values - without success.
SOR1 and SOR2 registers both show all 0s as expected.
So far, we have not found any register configuration or electrical design change that enabled us to establish a 100Mbps link with any link partner.
Attaching our electrical design for reference, we'd be happy for any pointers or debug advice we can try to overcome this.
Thanks in advance,
Ran.
