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DP83TC812R-Q1: DP83TC812R-Q1 debugging questions

Part Number: DP83TC812R-Q1

Hello Expert:

  Currently we are design DP83TC812R-Q1 as 100base PHY ,We i,plement the newest Linux driver a we are trying to debug link fail issues with some external realtek PHY devices in bootloader. we have some questions , 

Attached Link successfully V.S Link failed log file  , from log comparison between 0x0~ 0x1f the difference:

(1) BMSR (0x1) bit 2 : Link down.

(2) PHYSTS Register (0x10) bit 0: Link down

Questions:

(1) we reviewed MISR1(0x12) BIT(13) & BIT(10):  link_int & ms_train_done_int were different 

We would like to know how these two values are means for ? What does it mean if both of these values are 0? 

(2) BMCR(0x0) BIT(8):  Both situations of being able to connect and unable to connect are the same, BIT(8) being 1 indicates Full Duplex. This means that for the PHY->  it cannot perform a PAM handshake with the other PHY (If PHY using Realtek ), right? 

Thank you 

DP83TC812R link failed vs Successful Log.pptx 

  • Hi Roy,

    Is this issue occurring in Linux or in u-boot?  We should confirm that open alliance configuration script is being written using clause 22 indirect register access.

    (1) we reviewed MISR1(0x12) BIT(13) & BIT(10):  link_int & ms_train_done_int were different 

    We would like to know how these two values are means for ? What does it mean if both of these values are 0? 

    Bit 13: Indicates that a change in link status has occurred.

    Bit 10: Indicates that link training completed interrupt was set.

    A change in these values is expected after linkup.

    (2) BMCR(0x0) BIT(8):  Both situations of being able to connect and unable to connect are the same, BIT(8) being 1 indicates Full Duplex. This means that for the PHY->  it cannot perform a PAM handshake with the other PHY (If PHY using Realtek ), right? 

    This register will always show full duplex bit being set, regardless of link status.

    Thanks,

    Drew