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SN65LVDT125A: Desigining with SN65LVDT125A

Sv
Intellectual 655 points

Part Number: SN65LVDT125A
Other Parts Discussed in Thread: SN65LVDS125A

Hello Team,
We are planning to use the IC SN65LVDT125A in one of our products.
The use case seems little differnt from the intended application of the IC.

We have an MCU which acts as an SPI master. The SPI slave is another device and is conneted via cable.
So we are converting this single ended SPI to LVDS with LVDS driver SN65LVDS31PW and LVDS receiver SN65LVDS32PWR (for MISO signal).
At the slave side, these signals are converted to single ended from SPI with transcivers MAX9111EKA+T and MAX9110EKA+T.

The SN65LVDT125A will be used at the slave side to switch the slave with different masters in the test bench.
The output side (Y&Z) will be connecteed to the slave and inputs (A&B) will be connected to differnt maters via connectors and vice versa for the MISO signal.

 

 

 

 

1). Can you please confirm the logic compitability of SN65LVDT125A with SN65LVDS31PW, SN65LVDS32PWR, MAX9111EKA+T and MAX9110EKA+T. ?.

2). if the driver is not seleceted with (xDE pin) or the forst output channel (1Y&IZ) are seleceted for the input 1A&1B thosugh the ouput channel selcection pins, what will be the signal at the non selected output channels due to paracitic capacitance between input and output?.

3). 

Looking for your reply.

 

 

 

 

 

  • 0
    TI__Genius 14716 points

    Hi Sv,

    Can you share a schematic/block diagram of how you intend to use these devices? I'm a little confused with how these connections are being made and why you are using 2 different types of LVDS driver/receivers. 

    Regards,

    Matt

  • 0 in reply to Matt Smith
    Intellectual 655 points

    Hello Matt,
    Thank you for your reply.


    In the above image, one SPI master will be connected to the 1A/1B of the SN65LVDT125A.
    The second will be connected to the 2A/2B of the     SN65LVDT125A.

    The output (1Y/1Z) will be connected to the slave.
    Through the select lines, only one master will be connected to the SPI Slave.

    The SN65LVDT125A will be doing the job of an analog switch.

    With this setup, we can test multiple SPI masters with a single slave in a test bench.
    The SPI slave is a legacy part that uses the transceivers MAX9111EKA+T and MAX9110EKA+T.

    1). Can you please confirm the logic compatibility of SN65LVDT125A with SN65LVDS31PW, SN65LVDS32PWR, MAX9111EKA+T and MAX9110EKA+T. ?.

    2). if the driver is not selected with (xDE pin) or the first output channel (1Y&IZ) are selected for the input 1A&1B though the output channel selection pins, what will be the signal at the non selected output channels due to parasitic capacitance between input and output?.

    3). 

    Looking for your reply.

  • 0 in reply to Sv
    TI__Guru 67607 points

    Hi Sv,

    Today is a public holiday. Please help give some time for some feedback, thanks.

    Best Regards,

    Michael.

  • +1 in reply to Sv
    TI__Genius 14716 points

    Hi Sv,

    Understood. Thanks for the clarification. Please see below for my responses to your questions:

    1. Yes. Anything that adheres to the TIA/EIA-644 LVDS standard will be compatible with each other. 
    2. If any channel is disabled or unselected, the output will transition to be high-impedance and VOD will be 0mV. If you are wanting to know about crosstalk, we don't have that measured for this device, but the PCB layout and cable design will play a much bigger role in that than the device itself. 

    Regards,

    Matt 

  • +1 in reply to Matt Smith
    Intellectual 655 points

    Hello Matt,
    Thank you for your reply.

    1). I initially thought the device is like an analog mux but it is kind of a repeater. For analog mux, there will be a parasitic capacitance between input and output so the we will get a DC biased signal at the output even if the device is off.

    2). I believe the device SN65LVDS125A doesn't have an internal termination resistor. All the transceivers we are using are 100 Ohms

    3). The maximum SPI speed is 50MHz. I hope the device can work smoothly at this speed.

    4). Since SPI signals are unidirectional, this device will work there.

    5). Out of curiosity, will this device work for CAN and FlexRay?. CAN is 120 Ohms and FlexRay is 100 Ohms.
    CAN and FlexRay are bidirectional.
    So will the following setup with SN65LVDT125A work.

    The drivers 1 and 2 will be enabled and 3 will be enabled when CAN analyzer is required.

    Or the main CAN devices can be connected directly and the devices like CAN analyzers can be connected to the SN65LVDT125A  like this.

    Can you please comment on this?.

  • +1 in reply to Sv
    TI__Genius 14716 points

    Hi Sv,

    This device will not work for CAN or FlexRay. Those protocols have different physical layers than LVDS. As you mentioned, this device is a buffer, and it will only output LVDS signals which a CAN/FlexRay transceiver will have issues reading. 

    In regards to the 50MHz SPI clock, this device can support signal frequencies up to 750MHz. However, with SPI, the max frequency becomes a factor of overall loop delay, which is affected by things the propagation delay of all the ICs in the signal chain, cable length, and PCB layout. I would recommend reading this app note for more details: https://www.ti.com/lit/ug/tidued8/tidued8.pdf 

    Regards,

    Matt