TMS320C6748: Regarding the drive capability issue of the EMIFA interface of TMS320C6748

The device datasheet documents IOH and IOL in table 5.5.

The extremely long traces, together with the inter-board connections,  probably do need some buffering.

However, I suggest you model/simulate the signal path as part of your decision process. The IBIS models are available in the product folder on ti.com.

Be sure to consider the timing impact of this implementation. 

--Paul 

谢谢，请问下如果增加缓冲器的话，有没有推荐的缓冲器芯片，信号频率大概是100M，以及是否所有信号线都需要增加缓冲器。

Thank you. If we add a buffer, do you have any recommended buffer chips? The signal frequency is about 100M. Also, do we need to add buffers to all signal lines.

I don't have any specific recommendations.   

You will need to look at the impact of the buffer on timing to determine if more than just the bit/word clocks also need buffers.   

--Paul