SN65LVPE502A Differences From SN65LVPE502*

Daniel,

The SN65LVPE502A fixes all errata found on the SN65LVPE502CP.  I am attaching the errata for the SN65LVPE502CP and the application note for the SN65LVPE502A.  The major change with the SN65LVPE502A is the signals are now labeled as device-side and host-side connections. 

 3817.SN65LVPE502CP_Errata_SLLZ070.pdf

8231.SN65LVPE502A_Application_Note.pdf

Thanks,

Toni

Toni,

a) Thanks!

b) Does the relabeling of the pins imply that it (really) matters which side of the SN65LVPE502A gets connected to where?  Or was the relabeling done to just help keep signal-connection issues straight?

c) Per b) above, if the connections matter, why do they matter?

d) Per c) above, what is the detailed functionality difference between the signal flow from the Host RX inputs to the Device TX outputs, relative to the the signal flow from the Device RX inputs to the Host TX outputs, making labeling of each side necessary?

e) Per c) and d) above, what will happen if in a design (intended for e.g. the SN65LVPE502CP) a SN65LVPE502A is used but is wired in "backwards", what issues/problems may or will result?

f) Per b) and c) above, given that the connections to/from the SN65LVPE502A are more constrained than for the SN65LVPE502 and SN65LVPE502CP (per their pin names), does that imply that there really was previoulsy some assymmetry in play even for the SN65LVPE502 and SN65LVPE502CP, even though no mention of anything like that was made in their datasheets?  Or is a design (truly) free to "rotate" those ICs (the SN65LVPE502 and SN65LVPE502CP) around as may be desired, without regard to which side of the IC the host or device is connected to?

g) Given that neither DigiKey nor Mouser yet have the SN65LVPE502A available, how quickly can 25 or so samples be acquired for an immediate requirement?

h) Is an errata file available for the SN65LVPE502? 

Daniel,

My answers are below in red.

b) Does the relabeling of the pins imply that it (really) matters which side of the SN65LVPE502A gets connected to where?  Or was the relabeling done to just help keep signal-connection issues straight?  It really matter which side of the SN65LVPE502A  gets connected to host/device

c) Per b) above, if the connections matter, why do they matter?  The fix for the errata is required on the device side. The SN65LVPE502A fix was needed ASAP, so this was the only available solution for a quick spin.  Future parts will not have this limitation.

d) Per c) above, what is the detailed functionality difference between the signal flow from the Host RX inputs to the Device TX outputs, relative to the the signal flow from the Device RX inputs to the Host TX outputs, making labeling of each side necessary?  Circuitry was added to 'de-bounce' the noise caused by VBUS powered devices.  This de-bounce circuit is used for the device side.  Because the connection to the host does not change, this circuit is not required on the host side.

e) Per c) and d) above, what will happen if in a design (intended for e.g. the SN65LVPE502CP) a SN65LVPE502A is used but is wired in "backwards", what issues/problems may or will result?  If the SN65LVPE502A is wired 'backwards' you may see the errata described wor the SN65LVPE502CP where the redriver enables termination too early due to noise from a VBUS powered device.  There are plans for a SN65LVPE502B part that may be used if there is an existing design that is 'backwards'.

f) Per b) and c) above, given that the connections to/from the SN65LVPE502A are more constrained than for the SN65LVPE502 and SN65LVPE502CP (per their pin names), does that imply that there really was previoulsy some assymmetry in play even for the SN65LVPE502 and SN65LVPE502CP, even though no mention of anything like that was made in their datasheets?  Or is a design (truly) free to "rotate" those ICs (the SN65LVPE502 and SN65LVPE502CP) around as may be desired, without regard to which side of the IC the host or device is connected to?  There was no asymmetry in the SN65LVPE502 and SN65LVPE502CP devices.  They could be connected either direction host-redriver-device or device-redriver-host.

g) Given that neither DigiKey nor Mouser yet have the SN65LVPE502A available, how quickly can 25 or so samples be acquired for an immediate requirement?  Please give me your shipping address and I will get some samples sent to you.

h) Is an errata file available for the SN65LVPE502? I will need to look into this one.  It should also include the errata for the SN65LVPE502CP part.

Thanks,

Toni

Toni,

Thanks for the clear and detailed information in your reply.  Please let  me know how I can get you my shipping information without posting it here publically.

You mentioned that the SN65LVPE502A Device side was enhanced per the leaving-RX-Detect-mode-too-early issue.  How about the other issue that was addressed, the RX-termination-remaining-enabled-too-long issue: were both sides of the IC enhanced to address that issue, or just one side?  If just one side, which side?

Daniel,

The website should start accepting sample requests this week, so please enter your request through the ti.com website. 

The second errata, the RX-termination-enabled-too-long-issue, is fixed on both sides.  We normally observed this issue on the host side, but the fix is addressed on both.

Thanks,

Tonin

I don't feel that the original question was fully answered.  In particular, how is the  SN65LVPE502 (presumably the original part) different from the SN65LVPE502CP version?

Thanks,

Judd

Hi

Ti Guys,

The "description" section is identical between SN65LVPE502A and the SN65LVPE502CP.

What are the differences, if any, please?

I need to know which part to order. 

Thanks,

 Avishai

Hi.

I'm currently having trouble getting a SN65LVPE502A to work on a system. It is implemented on a board, the same way as the SN65LVPE502CP on its eval board (with a USB3.0 A and B connector on each side). When replacing our board with the CP eval board, everything works fine. Hardware design (schematics, decoupling, layout) has been done very carefully (ultra low noise supply, checked to be below -75dB on our board  from 0 to several GHz), careful diff pairs routing, impedance checked in PCB manufacturing. The only remaining difference between our board and eval board is the chip revision CP vs A but I can't find any clear difference in these parts description that would explain this.

On the eval board, pairs polarity is crossed compared to pins labels. It works fine. Is revision A polarity-agnostic aswell as revision CP? I would guess so but I have not found any mention about this anywhere and would like to make sure.

I also noted the recent relaese of a CP1 revision but could not find any mention of difference from CP to CP1. Could you give more details?

Thanks.

Hello Arnaud,

    Could you send me your schematics in order to start the debugging of the issue.

Best regards,

Diego.

diego.cortes@ti.com

Sure but, how do i proceed to attach schematic files to my answer and make sure these remain pretty confidential (even if there is no secret in the schematic around SN65LVPE502...)?

Hello Arnaud,

    The document will be handled as confidential information, also you dont need to send the whole doccument, you can send only the  part of the schematic regarding the SN65LVPE502. 

Regards,

Diego. 

Addressed by email.