I have a TL16C550D ACE being used for RS485 communication on a custom board that is controlled via a Virtex 6 FPGA. I seem to be having issues setting it up though. Right now I am feeding in a divided down clock of 14.285714MHz to the ACE. I am then waiting ~100us after the FPGA comes up to start setting up the ACE. On the rising edge of the 14ish MHz clock I setup the 8b data values and the 3b register address lines and make sure the WR is disabled, then on the next clock I enable WR.
The order I am doing things is:
1 - I setup line control reg (minus DLAB) for 8-N-1 and no break control on register 0x03
2 - I write the same value as above step, but with the MSb DLAB set
3 - I set the LSB Divisor Latch to a value of 8 on address 0x00 (a 14.285714MHz clock with a divisor of 8 = 115200 baud with 3% error)
4 - I repeat step 1 to clear the DLAB bit
5 - I write a 0xD9 to the data register and set the register address to 0x00
I see some data coming out of the ACE, but each bit seems to be running at 50ms (a baud of 20), so that is definitely not right. These leads me to think that my I/O lines are OK (CD, WR, etc.), but that I am not writing to the registers properly. Anyone see something I've missed?
