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DP83848 false carrier sense with capacitive coupling

Jeroen Ommering
Prodigy 180 points

Hello,

I have problems with a capacitive coupled link between a DP83848 and a Micrel KSZ8997 Ethernet Switch (with 5cm between the two devices on the same PCB). The link is up and most of the packets come through but I am experiencing 'cuts' in the connection that even TCP cannot 'repair' (once every 2 .. 10 seconds).

The two symptoms besides the cut are worth being mentioned: 

  • The Activity LED is almost constantly on, even if no traffic is sent
  • The 'False Carrier Sense Latch bit in the PHYSTS register is constantly set (after each read, I clear it by reading FCSCR)

The capacitive coupling is done as described in application note AN-1519: 49R9 termination resistors on all lines to 3V3 and 100nF capacitors.I am actually quite sure that the DP83848 is not the problem: in an earlier version of our board, we used another Micrel Switch (KSZ8995MA) and using the same capacitive coupling it all worked fine.

Other facts:  the MDIX is disabled, auto-negation is disabled, fixing to 100Mb/s and full duplex.  (On the Micrel switch, I cannot disable auto-negation but in a Micrel application note about capacitive coupling similar to the one mentioned above it is mentioned that the KSZ8997 was successfully verified to work)

Not (yet..) being an Ethernet expert, my problem is that I have no clue where to look. Could anybody give a hint on what is going wrong, considering the above mentioned symptoms?

Any help is very much appreciated!

Jeroen Ommering

  • 0
    TI__Mastermind 31600 points

    The fact that you are seeing constant indicators of false carrier could be an indication of a problem with the link.  Could you provide me with a schematic to review? 

    Do you have the equipment to probe the signaling during the problem condition?  Confirming the signal levels and waveshapes could be helpful. 

    On a different note, the configuration of the two devices might cause problems as well.  Per the IEEE specification, a device configured for auto-negotiation should resolve to 100Mbps full duplex via auto-negotiation with the partner.  If a device configured for auto-negotiation sees 100Mbps scrambled idles, it should parallel detect to 100Mbps half duplex.  A link with one partner configured for full duplex and the other partner configured for half duplex will have problems. 

    I would not expect a mismatch in duplex configuration to cause the problem you are seeing however unless there is packet traffic.  In the problem condition you describe, are one or both of the devices transmitting packets? 

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 180 points

    Attached you find the two relevant sheets of the schematic. On the first sheet you simply see the Micrel switch to which it is connected (to pins RXP4, RXM4, TXP4 and TXM4 on the right side of the U86. The important stuff is on the second sheet. The DP83848 is connected to a PIC32 which is not shown. That part is working however since I can configure the DP83848 and as said before I also get most packet across the link.

    Probing exactly when the problem occurs is hard since it occurs only ever 5 .. 10 seconds and I don't know where to trigger on. However, I attached two screen shots of the signals on the RD-/RD+ lines and the TC-/TD+ lines. It is hard for me to judge whether they are OK so your opinion will be helpful.(CH1 is the positive line but that hardly matters I guess. The two horizontal lines indicate a 1Vtt voltage)

    I'm not sure whether the problem occurs during packet transmission or reception. But I am sending data over the line (the PIC32 and DP83848 are 'slaves' in the sense that they mainly send data as a response of requests received from the PC behind the switch.

    Link problem.zip
  • 0 in reply to Jeroen Ommering
    TI__Mastermind 31600 points

    Could you indicate the positions of the probe connections for the screen shots of the TD+/- and RD+/- lines?  Where exactly were the measurements taken?

    Could you indicate the source of the 50MHz RMII clock to the PIC?  Could you also provide some screen shots of the 50MHz clocks as measured at the destinations (DP83848 and PIC input pins)?  What component is used for the 50MHz RMII clock reference to the Phy (XT3)?

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 180 points

    I measured on the traces that go to the TD+/- and RD+/- pins of the DP83848.

    The 50MHz clock comes from a Xtal oscillator (Farnell reference 1276652) and goes to both the PIC and the DP83849. I am unfortunately not able to make a screenshot of the signal because I am not in the office this week.

    The schamatic of PIC and DP83848 plus everything around it did not change since the previous revision that worked correctly. Only the other side of the capacitive coupling changed  (from Micrel KSZ8995 to KSZ8997)

  • 0 in reply to Jeroen Ommering
    Prodigy 180 points

    It finally all works well. The only thing that had to be changed was adding a few 22u ceramic capacitors on the 'analog' supply of the Micrel Ethernet switch.......

  • 0 in reply to Jeroen Ommering
    Prodigy 10 points
    Hi Jeroen. One to test your memory. I am having issues with capacitive coupling. Can you please clarify where you added the 22uF capacitors? Are you able to post an updated schematic, or spell out where they were added? Thanks in advance!
  • 0 in reply to Matthew Kerr
    Prodigy 180 points

    Hello Matthew,

    I suppose I'm too late with my reponse, but I saw it I added accidentally only now.
    I added one 22uF capacitor on the 2.2V supply to VDD/VDD-IO and one on the 2.2V 'analog' supply rail for VDD-RX / VDD-TX / VDD-RCV.
    Physically on the board, as close as possible to the switch of course. I have planes for these supplies on an inner layer.