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DS90UB925Q/DS90UB926Q I2C Clock stretching query

Other Parts Discussed in Thread: DS92LX2121, DS92LX2122

Hi,

I have recently been evaluating the DS90UB903Q / DS90UB904Q FPD-Link-III chip set; for which I have come across a limitation in the Ser/Des I2C bi-directional communication channel when configured in the Display Mode that results in the chip-set not being suitable for my application. A diagram of this previous set-up is as follows:-

The problem I expierienced has been shown in the attached image, which shows the communication via the Ser/Des devices @ 100 kHz .

With reference to this the problem was that after the AR1021 read address (0x9B) is sent, the Des after a short delay (≈20μs) generates it’s 8 clock pulses to read the data from the Slave (AR1021); however it was interrupted before completing the 8 clock pulses with the DES_SCL being pulled low (Understood to be the AR1021 attempting to clock stretch). The effect of this is that the data is regenerated back to the PICkit Serial analyser (Master) before completing the actual read causing timings violations and in-correct data being read. After posting this problem on this forum it was understood that when the serdes behaves as a master (DES in this case), the device does not support clock stretching from a slave device. The chipset’s internal master I2C controller expects to solely control the bus with the attached slave device .The 903/4 was highlighted as being a 1st gen FPD-Link III chipsets with bidirectional interfaces using I2C which has limited bus management capabilities (ie multi-master, arbitration, etc) and these features were mentioned as being offered in our other chipsets such as DS90UH925/926

There was no option to add a delay into the read operation of the Des, and the only way I could configure the DS90UB903Q / DS90UB904Q to function correctly with the AR1021 was to program the internal pre-scalar register in the DES to the minimum speed 11 kHz SCL speed setting.

Can somebody please advise if the DS90UB925Q / DS90UB926Q and DS92LX2121 / DS92LX2122 chipsets supports full clock stretching at the Des and offers the functionality to solve my problem before I order evaluation kits ?

Thanks in advance

Lee Smith

  • Hi Lee,

    Based on the information I received, the DS90UB925Q/926Q will support I2C clock stretching from a slave device when the chipset is operating as a proxy master. The DS92LX2121/2122 will not support slave clock stretching; as its functionality is similar to DS90UB903/4.

    Dac Tran

    SVA APPS