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TLK100 Questions

Other Parts Discussed in Thread: TLK100

I have questions on the TLK100.


1)     From a power on reset (POR), does the PHY require that the clock is stable as it does for the Hardware reset (using the reset PIN). See data sheet section 9.6.2 RESET TIMING.

2)     For a hardware reset, can table9-2 reset timing be correct? It states that the reset pulse can be minimum of 1 us but states that it must low while the clock is stable for 1msec? What is it?

3)     Are all the hardware strapping latched the same on a POR as for a hardware reset? The documentation is unclear on the latching on a POR, please advise.

  • Paul,

    I have moved your post to the Ethernet forum. To help with better supporting and tracking your future questions in Ethernet, please post any new Ethernet related questions into this forum.


  • Hi Paul,

    1. the PHY requires a stable clock prior to the 200us before reset disengage (power on reset)
    2. In table 9-2 the description (test conditions) is indeed a bit confusing. bottom line is if you HW_RESET the phy the minimum time for reset staying low (width of reset_n) is 1us. just make sure the clock is stable at least 1ms prior to externally resseting the PHY.
    3. latching is done each time HW_RESETN is disengaged. and after POR as well.