I have questions on the TLK100.
1) From a power on reset (POR), does the PHY require that the clock is stable as it does for the Hardware reset (using the reset PIN). See data sheet section 9.6.2 RESET TIMING.
2) For a hardware reset, can table9-2 reset timing be correct? It states that the reset pulse can be minimum of 1 us but states that it must low while the clock is stable for 1msec? What is it?
3) Are all the hardware strapping latched the same on a POR as for a hardware reset? The documentation is unclear on the latching on a POR, please advise.