I'm am trying to configure DP83630-EVK to output Pulse Per Second (PPS) on one of the GPIO ports.
I am using an FPGA based embedded system and greatly reduced EPL C library to configure the DP83630-EVK.
I use the following configuration, from Software Design Guide and C Software Reference Library:
PTPEnable( pEPL_HANDLE, FALSE); PTPClockSetRateAdjustment( pEPL_HANDLE, 0, FALSE, FALSE); //dolje PTPClockSet( pEPL_HANDLE, 1, 0); PTPSetClockConfig( pEPL_HANDLE, CLKOPT_CLK_OUT_EN, 0x0A, 0x00, 8); PTPEnable( pEPL_HANDLE, TRUE); //gore // Configure Trigger 0 for PPS – only perform if using PPS PTPEnable( pEPL_HANDLE, FALSE); PTPSetTriggerConfig ( pEPL_HANDLE, 0, TRGOPT_PERIODIC|TRGOPT_NOTIFY_EN, 9); PTPArmTrigger( pEPL_HANDLE, 0, 10, 0, FALSE, FALSE, 500000, 0);
After this I expect to see a PPS at GPIO9 but it doesn't happen. Only change is a pulse that appears at CLK_OUT pin (pictures bellow).
Questions:
Am I wrong to expect PPS output after this configuration?
Is GPIO9 available for output?
Additional information:
DP83630-EVK jumpers used:
J12 - USB_3v3 J33 - auto-negotiation
J3 - PMDIO_MII J36
J4 - PMDC_MII J39
Reg_val after configuration:
PHY_PG5_PTP_TRIG: 0x5900