a) It is my understanding that the SN65LVPE502CP actually supports the CM Mode functionality of the earlier SN65LVPE502 part, even though the datasheet labels the CM pin (Pin 14) as RSVD. Please confirm that this is the case.
b) Does the SN65LVPE502CP respond to changes in the CM pin while the EN_RXD pin is high (enabled), or is it expected/required that the CM pin remain static before and/or during and/or after EN_RXD is asserted and later deasserted?
c) If the SN65LVPE502CP expects/requires the CM pin to be stable from some time before EN_RXD is asserted, while EN_RXD is asserted, and through some time after EN_RXD is deasserted, what setup and hold times for CM are required relative to the rising (assertion) and falling( deassertion) edges of EN_RXD?