This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH0366 problems at 2.97Gbps, low temperature.

Other Parts Discussed in Thread: LMH0366

We developed a 6-channel SFP transceiver board for a customer using the LMH0366 as re-clocker. Our experience so far...

At lab ambient temperatures (20degC), the devices work as expected for SD and HD data rates. At 3G rates, here is excessive jitter introduced by the re-clocker but it can be fixed by writing the special register values as described in an earlier post...

"1.          Register 0x19 bits 4:2 should be changed from 000 to 111.

2.           Register 0x0A bit 6 should be changed from 0 to 1.

3.           Register 0x1C bit 6 should be changed from 0 to 1."

At low temperatures (we tested at -40degC, our customer reported problems below 0degC), the above statement holds with one exception: HD and 3G data rates do not lock with the special register values. Operating the devices with default settings we achieve lock and writing special register values then improves jitter at 3G rates (SD and HD again seems OK without having to write special register values).

Based on numerous posts on this subject on this forum as well as observation during testing it seems as if the various reclockers' PLLs are interfering with each other. Due to space constraints the components are placed fairly close to each other but we have tried to adhere to all recommended guidelines in the datasheet. In an effort to improve performance (i.e. operate the devices with default settings over all data rates at all temperatures) it would be helpful if you can assist with answers to the following:

1. The register writes: I've found a different post (as far as I can ascertain also referring to the LMH0366) specifying new values for registers 0x0A, 0x1C and 0x13. Are we using the correct registers in our application - being 0x19, 0x0A and 0x1C?

2. What happens to the jitter attenuation if using the special register values? I assume performance to decrease as the loop bandwidth is increased. Can you please confirm?

3. The dev kit (SD3GDAIII) schematic indicates a 4.7uF capacitor being used for the loop filter. This is significantly different from the datasheet recommendation of 56nf. Will an increase in the loop filter capacitor beyond 56nF help?

4. Is there a known coupling mechanism involved when placing a number of LMH0366 devices close to each other - i.e. does the noise enter through the VCC pin, the VEE pins or is the device susceptible to radiated emissions from neighbours (i.e. will a small enclosure over each device help)? We are already using a dedicated 2.5V LDO (LT1963) to supply all devices.


Riaan

  • Hi Riaan,

    1). The settings you have outlined are correct.

    2). These settings increase the loop bandwidth and thus enables the device to track injected noise. With these settings, the output jitter could increase(as you noted).

    3). This should be 47 nF not 4.7 uF. However, i don't think changing to 47 nF would make a change here.

    4). Noise coupling occurs when we have devices in close proximity. There could be multiple paths through supply, GND, or a signal connecting two LMH0366 devices with one another. So i don't think small enclosure could help.

    Can you please try a 4.7pF Cap from pin 22 to GND? This would attenuate noise being injected into the loop filter. Please note GND for this Cap should not be inductive. Hopefully you have GND fill or GND around this pin.

    Regards,,nasser
  • Hi Nasser

    Thanks for the reply. I will try the 4.7pF capacitor and post results.

    Regards

    Riaan
  • Hi Nasser


    I've implemented the 4.7pF capacitor on two adjacent channels with the following results (all without special register configuration):

    a. Jitter at SD and HD is slightly improved and well within specification. I can use any combination of sources (SD, HD or 3G) on the other reclockers as well as using different generators (not using a common clock - see below).

    b. Jitter at 3G is improved. If the two reclockers are driven from the same source the alignment jitter is approximately 0.1UI as opposed to 0.4UI without the capacitor. The observed jitter withouth the 4.7pF cap is non-synchronous to the video line frequency. If I use two different generators (i.e. different source clocks) and I apply 3G to both reclockers I still do not meet specification (even with 4.7pF capacitor). The jitter in this case seem to be synchronous to video line frequency.

    I believe that the 4.7pF capacitor is effective in removing a source of external interferance that causes jitter. The remaining jitter seems to be from coupling between the two reclockers if they are driven from two different 3G sources with slightly different clock frequencies. Next step will be to find and isolate the common coupling path.

    Regards

    Riaan

  • Greeting Riaan,

    Could you please include special register configuration while you have 4.7 pF capacitor on pin 22 to GND? Also, please make sure 4.7pF GND is not inductive.

    Regards,,nasser
  • Will do - would you mind if I e-mail you in this regard?
  • Sure. Please go ahead and e-mail in this regard.

    Regards,,nasser