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TLK100 - pulling up TXD1-3 pins at reset makes the device unusable

Other Parts Discussed in Thread: TLK100

Hello,

We are using the TLK100 device in many designs, but in one of our new designs we have found a problem. We are now interfacing the TLK100 with a Marvell 88E6176 gigabit switch with MII interface. For the 88E6176 the TXD0-3 pins are boot strap pins, so for proper operation we had to strap these pins in the following way: TXD0 and TXD2: 4.7k to ground, TXD1 and TXD3: 4.7k to 3.3V.

The problem is that with the following configuration, the TLK100 goes to an unusable state with strange behaviour. E.g. after reset, the PWRDNN/INT pin of the TLK100 goes to low state, if the MDC input is high. (however, both pins should be intputs).

We found out, that the problem is caused by the pull-ups of the TXDx pins, so we made measurements with another design, where the TLK100 is connected to an microcontroller with MII. The result of the measurement was the following (TXDx means a pull-up on the specific TXD pin): if (TXD3)*(TXD1+TXD2)=1, then the TLK100 is unusable.

In the datasheet (latest, rev B) there is no information about any strap configuration of these pins in the Configuration (chapter 3) section, however in the Pin Descriptions (chapter 2) the in the TYPE column for the TXDx pins it is written "IS" which means Input and Configuration. In the "TLK100 External Voltages EVM" user's guide, on page 9 of the schematic there are ignored pull-up and pull-down resistors for TXD1-3, so it seems that there is some strap function on these pins that is not discussed in the TLK100 datasheet.

Can you provide some information about the issue? What are these pins are used for? How to use the TLK100 with a device, that needs strapping of TXD pins?

Thank in advance:

András

  • Hi Andras,

    You see that MDC goes high after the RESET and that PWDN_INT goes low? Just wanted to clarify.

    We do not put strap configurations on input pins, but I will check to confirm.

    What happens if you apply a second RESET after observing the unusable state? Is there any recovery identified besides removing the pulls?

    Kind regards,
    Ross
  • Hi Andras,

    I have confirmed the behavior you describe on my bench. This was also confirmed by looking back at my notes. The TLK100 has a few configuration straps on the TX pins to place it into certain test modes. The options are to either remove the pull ups on the TX pins or to apply a RESET after the MAC is up and to ensure the TX pins are being driven LOW during the PHY RESET.

    Kind regards,

    Ross

  • Hi Ross,

    Thanks for the testing and the confirmation. Is it possible that there are other strap pins on the chip that are not mentioned in the datasheet? I would like to avoid future problems.

    I think this information about the test mode strap pins should be mentioned in the datasheet, so other users can make appropriate designs. In our design the reset of the MAC and the PHY is shared, so we have to redesign the board to apply the workaround you suggested.

    If you can do a fix on the datasheet, I would like to mention another bug in the datasheet about the MII_COL/PHYAD0 pin. On page 8 of the datasheet it is written that the pin is internally pulled LOW, but on page 7 it is written that this pin is pulled HIGH. Based on our measurements this pin is pulled HIGH. On page 15 (address configuration example) the figure is correct, but the text written for the figure is incorrect. This issue has been already mentioned here in the forum: e2e.ti.com/.../539155

    Best regards,

    András

  • Hi Andras,

    Those are the only other pins that have strap configurations that are not mentioned in the DS. I have filled a change for this yesterday and it will be updated in the DS.

    The other issue you mention is documented as well and is also in the process of being updated. Thank you for this feedback. Errors like this are not intentional and I appreciate your patience and help.

    Kind regards,

    Ross