DS16EV5110 : minimal input differential voltage swing

Further info: in particular the Clock signal.
we are observing that the internal PLL is locking on a 100mV ptp input clock signal (LOCK pin is high), but resulting clock is not outputted by the device

Hi Thomas,

Do you know the approximate attenuation characteristics of the cable assembly?  What is the clock amplitude at the launch side of the cable? If the input clock signal is only 100mV peak to peak I fear the attenuation is quite high.

Regards,

Lee

Hi Lee,

The total cable attenuation is indeed quite high.
The source diff voltage swing is 400mV, after coupling losses and cables losses, there is +- 100-200mV ptp remaining. (depending on setup)
The strange thing we observe is that the lock pin is high, indicating the internal PLL is locked, but output clock signal is only 50mVptp.
The data signals are actually getting trough (500mVptp) but our receiver cannot lock onto this low clock signal.
When we use another source, where the equ sees 400mV ptp, all is fine.
So the lower limit of acceptable diff voltage swing is somewhere between 100-150mV?

Do you have an explanation why the output clock is low while the device indicates a locked PLL?

Thanks in advance,
Thomas

Thomas,

Please attach measurements of the clock waveform at the source and clock receive waveform at the DS16EV5110.  If possible take the same measurements of the data signals too.

Thanks,

Lee