• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 711 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Multi drop interfacing design

Swaminath Katte
Prodigy 50 points
Other Parts Discussed in Thread: SN65LVDT41, SN65LVDT14

Hi,

I need to interfacing different ICs of different PCB cards to the CPU card using SPI bus, which increases distance between master CPU and slave ICs. Therefore I want use LVDS for long distance communication with multi-drop topology using LVDS IC SN65LVDT14 and SN65LVDT41.
 Is it possible to design multi -drop topology using this LVDS SN65LVDT41 IC? Please suggest any circuit  design idea.

Thanks,

Swaminath

  • 0
    TI__Expert 3175 points
    Hi Swaminath,
    I understand SPI interface is used between master and slave in a point-to-point applications. For multiple slave devices, typically they are daisy chained.
    It is not clear to me how you plan to use multi-drop from/to many slave ICs, can you clarify?
    regards,
    TK Chin
  • 0
    TI__Mastermind 43795 points

    Hi Swaminath,

    Since you are interfacing a CPU and multiple cards I will assume there are several SPI slave devices attached to this bus.  SPI operates at very low speeds, I would be surprised if any additional LVDS buffering was required even over many feet of signal trace length.  Also, SPI uses bi-directional communication on the SCL and SDA connections.  It would be difficult to control this directional signaling with the LVDS transceivers. 

    Regards,

    Lee