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DS90CF388A - latency between input to output data

Ryuji
Guru 20090 points
Other Parts Discussed in Thread: DS90CF388, DS90CR484, DS90CF388A

Hello,

Could you please let me know the latency of DS90CF388?
I would like to know the delay time from input the data to output the data.
The input clock is 74.25MHz.

Best Regards,
Ryuji Asaka

  • 0
    TI__Mastermind 29655 points

    Hi Asaka-san,

    We do not have any characterization data available for the latency of the DS90CF388A. However, I was able to reference a similar device that uses an identical package that is comparable as a reference point. For this reference, I looked at the DS90CR484.

    The DS90CR484 states that the propagation delay is dependent on the TCIP parameter, which is simply the TxCLKIN period:

    Thus, I expect the min/typ/max latency for the DS90CF388A at 74.25 MHz to be around:

    Min = 3 / 0.07425 + 4.0 = 44.4 ns

    Typ = 3 / 0.07425 + 4.8 = 45.2 ns

    Max = 3 / 0.07425 + 6.5 = 46.9 ns

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Guru 20090 points

    Hello Michael san,

    Thank you for the information.
    I would like to confirm the following.
    Is the propagation delay correlated with Package size?
    And, is the DS90CR484 design same with the DS90CF388A?

    Best Regards,
    Ryuji Asaka

  • 0 in reply to Ryuji
    TI__Mastermind 29655 points
    Hi Asaka-san,

    Propagation delay is partially affected by package size. Even if there were no components within the package and just a simple wire connecting a pin on the left side of the package to a pin directly on the right side of the package, it will take longer for the signal to traverse the package than for a similar, but smaller dimension package. However, a large determining factor is the latency introduced by the gates switching within the IC. Therefore, to make a reasonable comparison with another device, both the package and the IC design should be as equivalent as possible.

    The DS90CR484 and DS90CF388A are based on the same silicon design.

    Regards,

    Michael