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XIO1100 NAND Tree Testing

Other Parts Discussed in Thread: XIO1100

For the XIO1100, it is a shame that no real 3.3V JTAG port was included, especially given that such is part of the PCI Express interface, TI has been very active in JTAG testing, and there are so many parallel interface lines to be tested between the XIO1100 and connected FPGA. I just found out about the "NAND Tree Test" capability. Is the TRST# signal necessary for NAND tree test setup, or can it just be hard wired high (inactive)? Thanks for your help...

  • Bruce,
    I am checking this internally. I will come back to you as soon as I have more details on the requirements for TRST.
    Thanks,
    Jorge
  • Bruce,

     

    My apologies for the delay on this response.

     

    Typically, TRST is not mandatory for JTAG.  The TAP controller can be reset to default state by TMS = 1 and toggle CLK.  If you don’t use TRST, then SW must transition TAP controller to reset state.


  • Thank you Jorge for your reply.  I realized after I asked the question that if the XIO1100 is always going to be connected to a JTAG port which can clock in TMS=1 (at least five times) and thereby drive the JTAG TAP state machine to the Test-Logic-Reset state, then there is indeed no need to drive TRST# (other than to tie it inactive).  However, if there is any chance that the XIO1100 could boot up without a JTAG port driver being present, then the only way to guarantee proper XIO1100 operation is to tie TRST# active low, to force the JTAG TAP state machine into Test-Logic-Reset state and prevent NAND Tree Testing from becoming active accidentally.  On our XIO1100 prototype board we have indeed tied TRST# active low, so for now the NAND Tree Testing is disabled.  You may close this case.