For the XIO1100, it is a shame that no real 3.3V JTAG port was included, especially given that such is part of the PCI Express interface, TI has been very active in JTAG testing, and there are so many parallel interface lines to be tested between the XIO1100 and connected FPGA. I just found out about the "NAND Tree Test" capability. Is the TRST# signal necessary for NAND tree test setup, or can it just be hard wired high (inactive)? Thanks for your help...