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About EQ spec of DS100BR210

Guru 18390 points
Other Parts Discussed in Thread: DS100BR210, DS100BR210EVK, DS100BR410

Please let me know about two points below for DS100BR210.

※Evaluating DS100BR210EVK, 2.94Gbps, and cable are AWG-30 3m and AWG-26 6m(Total 9m)

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①When increase EQ level(Pin setting), EQ Lebel: 9(EQA1=F, EQB1=0)is reduce effect.

Is EQ gain is not monotony increase?

Please see attached below; 

※Horizontal line: EQ Gain

 Vertical line: Upper(Non-emphasis), Middle(2.5dB emphasis), Lower(6dB emphasis)

For example, Upper/20dB is increase jitter, but Upper/23dB is reduce jitter.

②About below block diagram, I think that EQ-Gain is only EQ point, and output signal is amplitude from two output buffer, is it correct?

And, is there spec information of EQ spec graph(Horizontal: Frequency, Vertical: Gain) and buffer Gain?

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Best regards,

Satoshi

  • Hi Satoshi-san

    The boost setting "F0" has lower boost at 1.5 GHz.  So you are correct, at lower frequencies the sequence of CTLE gain settings is not always in order.  You can see this detail in the chart below.

    Datasheet
    EQ Level
    Pin
    Setting
    Boost
    @ 1.5 GHz
    Boost
    @ 2.5 GHz
    Boost
    @ 3.0 GHz
    Boost
    @ 3.5 GHz
    Boost
    @ 4.0 GHz
    Boost
    @ 6.0 GHz
    1 00 2.5 3.5 3.7 3.8 3.9 3.1
    2 0R 3.8 5.4 6.0 6.4 6.7 6.8
    3 0F 5.0 7.0 7.6 8.1 8.4 8.3
    4 01 5.9 8.0 8.6 9.0 9.3 9.1
    5 R0 7.5 10.3 11.3 12.1 12.8 13.8
    6 RR 6.9 10.2 11.5 12.8 13.9 16.2
    7 RF 9.0 12.4 13.6 14.5 15.3 15.9
    8 R1 10.2 13.8 15.1 16.0 16.7 17.1
    9 F0 8.5 12.6 14.4 16.0 17.5 20.8
    10 FR 11.7 16.2 17.9 19.2 20.4 21.8
    11 FF 13.3 18.4 20.2 21.6 22.8 23.6
    12 F1 14.5 19.9 21.7 23.1 24.3 24.7
    13 10 14.4 20.5 22.9 24.8 26.4 28.1
    14 1R 16.1 22.3 24.6 26.4 27.9 29.2
    15 1F 17.6 24.4 26.8 28.7 30.2 31.0
    16 11 18.8 25.8 28.3 30.1 31.6 31.9

      

    Best Regards,

    Lee

  • Lee-san

    Thank you for data.
    Sorry for addition, is DS100BR410 the same spec?

    Best regards,
    Satoshi
  • Hi Satoshi-san,

    The DS100BR410 is not exactly the same, but it is very similar. 

    Regards,

    Lee

  • Lee-san

    Thank you for reply,

    Is there Gain chart for DS100BR410 near the case of DS100BR210?

    In the datasheet, EQ Gain spec are a little difference by DS100BR410 and DS100BR210/
    If there EQ Gain spec for DS100BR410 or calculation method, please let me know.

    Best regards,
    Satoshi
  • Satoshi-san,

    We do not have the full table for the BR410.  The architecture of the circuits is the same and the gain values are similar.

    The control register in SMBus for both devices is the same.  Bits [1:0] = 00 -> 11 (stage 1), Bits [3:2] 00 -> 11 (stage 2), Bits [5:4] 00 -> 11 (stage 3), Bits [7:6] 00 -> 11 (stage 4).  Each stage has 4 levels of control.  It is recommended that the equalizer gain is increased in the begining stages first to minimize Rj accumulation. 

    As you have seen in your testing, some equalization values are a better match to your application than others.  So the overall jitter result can be slightly non-monotonic even though the peak gain progressing through the settings is monotonic.  

    Regards,

    Lee