Hi,
My customer is considering DS110RT410 for 10Gpbs Ethernet.
They have questions about DS110RT410.
When reading the explanation of "7.5.8 Overriding the CTLE Boost Setting" in the data sheet, the following contents are written.
At divider values of 4 and 8, the CTLE boost settings used will come not from the values in register 0x03,
and 0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates.
The description of channel register 0x3A listed in Table 15 has the following description.
During adaptation, if the divider setting is >2, then a fixed EQ
setting from this register will be used. However, if channel register
0x6F[7] is enabled, then an EQ adaptation will be performed
instead
Set "1" to register 0x6F[7], but cleared to 0 when reading the this register.
[Q1]
Is this register write only?
[Q2]
If it is write only,
please tell us a method to check the operation of adaptive CTLE mode even by dividing values of 4 and 8 by setting this register to "1" ?
Best Regards,
Hiroaki Masumoto
