Other Parts Discussed in Thread: LMH1981
I use the chip for genlock and clock generation for our FPGA.
The chip gets an external tri level sync (1080i59).
We use the lmh1981 sync sepeactor.
All settings are done accoring to the manuals.
The chip is programmed according to the manual, including the special PLL initialization sequence for fractional framerates.
All works fine, but for 1080i59 we see an instable TOF position.
In most cases it is correct (as expected with 0 line delay, top of field).
In 20% we got a lock with (exact) +5 lines offset.
(Note: V-sync is 5 lines long....)
We see the offset with a scope (measured vsync from the separtor vs. the TOF output).
Strange: All progressive modes and "non" fractional seem to work correct.
Any ideas, how to make it stable?
