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DS32EL0421: ds32el0421

user5038588
Prodigy 30 points
Part Number: DS32EL0421
Other Parts Discussed in Thread: DS32EL0124, , DS32ELX0124

Support Path: /Reference designs/Technical support help for a specific technical issue with a reference design/

Hi,we use this way to tansmitter data: image sensor-->ds32el0421-->ds32el0124-->FPGA.

Now,we already get correct clock of image sensor. Both ds32el0421and ds32el0124's  "lock" singnal are low. But  we can't get data of image sensor,the data is always kept "0" in FPGA. 

We try to configure the input singals of "RS" and "DC_B" of ds32el0421 again and again, the results is dissappointed !

We enable Txin[0:4]  of  ds32el0421 !

We have no way to resolve problem. We need your help !

Thanks a lot!

  • 0
    TI__Intellectual 2915 points
    Hi,

    It is challenging for us to determine what is the cause behind this. Can you provide a schematic or let us know what the setup is between FPGA and DS32EL0124?

    There are couple of experiments we would like to check first.
    • DS32EL0124 powers up first then input data stream
    • Eye diagram at the input of DS32EL0124. Does the input jitter meets 0.3 UI ?
    • RxOUT 4+/- and RxOUT0-RxOUT3 status

    For example, it is important to keep the TXIN4 parallel input (Data Valid Input) to the transmitter high for 110 LVDS clock periods to allow the deserializer to lock properly. Also, it would be good for us to know whether any signal conditioning is being applied at the transmitter output. If the signal is overequalized, this can present issues for the DS32EL0124 to achieve lock, and it may be possible that a more transition-dense pattern, such as a combination of K28.5 and Dxy.z words, is creating a scenario that the DS32EL0124 can remain locked.

    Do you have jitter characteristics of the clock source? This would be PCLK input to the serializer.
    What are the characteristics of the cable(s)? How long are the cables? Do you know the attenuation / loss of the cables?
    Have you tried to reduce the cable length? What are the results?
    Is the layout optimized for 100 ohm differential impedance?
    Have you observed the LOCK output of the deserializer? Does the device become unlocked when you observe the display jittering?

    Regards,
    Dennis
  • 0 in reply to Dennis Wu
    Prodigy 30 points
    Thank you ! I had made it. I just kept DC-B high for 0124 and 0421, everything is ok.General speaking, Dc-B is just to solve AC couple, but we almost use dc couple.
    Here is the datasheet from 0124,I get idea according to these material.From datasheet,i know why rxout[0:4] always kept "0".

    DC-BALANCE DECODER
    The DS32EL0124 and DS32ELX0124 have a built-in DC-balance decoder to support AC-coupled applications.
    When enabled, the output signal RxOUT4+/-, is treated as a data valid bit. If RxOUT4+/- is low, then the data
    output from RxOUT0 - RxOUT3 has been successfully decoded using the 8b/10b coding scheme. If RxOUT4+/-
    is high and the outputs RxOUT0 - RxOUT3 are high then an invalid 8b/10b code was received, signifying a bit
    error. If RxOUT4+/- is high and the outputs RxOUT0 - RxOUT3 are low then an idle character has been
    received. The default idle character is a K28.5 code. In order to properly receive other K codes, they must first be
    programmed into the deserializer via the SMBus. The SMBus registers allow for only a single programmable
    character.
    Copyright