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SN65LVDS117: IO voltage compatibility with 1.8V

Nanjunda M
Expert 2485 points
Part Number: SN65LVDS117
Other Parts Discussed in Thread: SN65LVDT386

Hi,

We are planning to connect the LVDS pins of Kintex 7 FPGA to 1A and 1B input pins of SN65LVDS117DGGR.
The implementation is shown in a block diagram attached with the query.

New Microsoft PowerPoint Presentation.pptx

Regarding this connection I have 2 queries :

1. The FPGA LVDS pins reside in 1.8V Bank.The Supply voltage of SN65LVDS117DGGR is 3.3V. I have doubt in IO level compatibilities in this connection.
I was not able to understand the Figure 1 and Table 2 in the datasheet of SN65LVDS117DGGR (see Image 1) and I was unable to compare it against the Output characteristics of Kintex 7 FPGA (see image 2).
Can you confirm whether this connection is possible, whether the output characteristics of FPGA and Input characteristics of SN65LVDS117DGGR are matching?

2. We currently did not provide any termination for LVDS inputs of SN65LVDS117DGGR.In the datasheet, the termination details for all types of IO standard is mentioned except for LVDS. Please inform is any 100 OHM parallel termination or any other type of termination is required for LVDS inputs on 1A and 1B.

Regards,

Nanjunda M

  • 0
    Expert 2485 points

    Hi,

    Can anyone please help us with suggestions on above queries.

    Thanks & Regards,
    Nanjunda M

  • 0 in reply to Nanjunda M
    TI__Intellectual 2915 points
    Hi Nanjunda,

    The input voltage characteristic of SN65LVDS117DGGR are matching with the LVDS output from FPGA. I don't think you need to do AC coupling in between. You may connect FPGA directly to SN65LVDS117DGGR.

    You will need 100ohm termination at the inputs of LVDS.

    Dennis
  • 0 in reply to Dennis Wu
    Expert 1230 points

    Hi,

    Thank you for the response. This query is again raised in another project.

    Understood your point, but one more doubt we have :

    In FPGA datasheet the 1.8V LVDS section mentioned VOH and VOL. Similarly the datasheet of  SN65LVDT386DGG also mentions VIH and VIL.

    We are confirmed that the LVDS Characteristics are matching between these 2 devices (VID vs VOD and VICM vs VOCM). But tthe VIH vs VOH, VIL vs VOL are not matching exactly. For LVDS signals whether we need to consider this as an issue or can we proceed with the confirmation on VID and VICM?

    FPGA LVDS OUTPUT Characteristics :

    SN65LVDT386DGG:

  • 0 in reply to vijetha hn
    Expert 2485 points
    Can anyone please reply.

    Thanks & Regards,
    Nanjunda M
  • 0 in reply to vijetha hn
    TI__Intellectual 1810 points

    Hello Nanjunda,

    All LVDS receivers, if fully compliant to the LVDS standard should support any input voltage level between 0V and 2.4V on its input terminals. In your application scenario, the maximum input voltage level will result when the FPGA transmits with the maximum output common-mode voltage, VOCM = 1.425V with the maximum output  differential amplitude, VODIF = 600mV. In that case the maximum input voltage will be 1.425 + 0.6 = 2.025V which is below 2.4V and within the range supported by SN65LVDT386. The minimum input voltage level will result when the FPGA transmits with the minimum output common-mode voltage, VOCM = 1.000V with the maximum output  differential amplitude, VODIF = 600mV. In that case the minimum input voltage will be 1.000 - 0.6 = 0.4V which is above 0V and within the range supported by SN65LVDT386.

    There is no incompatibility between the output and input voltage levels in your use-case.

    Best regards,

    Hassan.