Hi Team,
Do we have maximum rise and fall time of HVDA551-Q1 differential output signal can share with the customer? The datasheet only mentioned the typical value of these specs.
Best Regards,
Nick Dai
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Hi Team,
Do we have maximum rise and fall time of HVDA551-Q1 differential output signal can share with the customer? The datasheet only mentioned the typical value of these specs.
Best Regards,
Nick Dai
Nick,
In the datasheet, the rise and fall times for CANH and CANL were measured using the following circuit:
With 60 ohms termination resistance and 100pF on the bus. The real max and min will depend on the application and how much loading that entails (number of transceivers on the bus, filtering, etc.), but I have found the maximum and minimum rise time values for this loading case from a characterization lot
Because the differential rise times are driven, this is a parameter that can be characterized. You don't see fall times in characterization data because the differential fall times are only effected by device input capacitance and impedance, and cable capacitance, and since the circuit to measure this parameter for the datasheet is defined, this value is given.
In general, the loading on the bus itself (capacitive and resistive) is going to have more of an effect on rise and fall times than anything inherent to the device, which is why you don't see a max or a min of this parameter in the datasheet. The rise and fall times are limited by on your message rate and how much loop delay you're allotted, and isn't defined by a specification.
Let me know if you have any more questions about the bus signals, or anything else about CAN.
Regards,
Hi Eric,
Thanks for your support.
Do we have data about the max load(resistor and capacitor) HVD551Q1 can accept,will high load cause output distortion?
The customer wants to know the maximum rise and fall time in 125kbps、250kbps、500kbps、1Mbps data rate they should follow?
Best Regards,
Nick Dai
Nick,
The maximum bus impedance is dependent on the ability of the driver to provide 5V differential signal across the termination resistance, which is defined by the CAN spec, along with sinking/sourcing all of the leakage current on the bus. The leakage current is the result of the input resistance of the transceivers on the bus, so you're limited to how many nodes can be in parallel. Different transceivers have different input resistances, but most modern transceivers allow for at least 120 different nodes allowed on one bus.
So the driver on the HVDA551-Q1 has an output current capability of 70mA max at 5V in normal mode when driving dominant. If you go beyond this 70mA, the device will start to have trouble driving the 5V differential signal along the bus.
For bus capacitance, contributions are going to come from each transceiver on the bus, along with how far apart they are from each other, any pins, connectors, traces, any filtering or protection devices, and any other physical connections on the bus. There's not a specific value that you will need to look out for, but too much capacitance will round off your driven edges, and cause the falling edges to decay too slowly.
An informative application note going into more detail about this, and the bus capacitance is located here.
For the maximum rise and fall times, check this post for an explanation, but in general, the transition should occur within 25% of the bit width. That is, for 125kbps, bit width is 8us, so the waveform would need to to transition from recessive to dominant within 2us, for 250kbps it should transition within 1us, for 500kbps it would be 500ns, and for 1Mbps it would be 250ns. The application note I linked earlier in this post also talks about bit timing requirements.
Please let me know if you have any more questions.
Regards,