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SN65MLVD082: IBIS simulation for SN65MLVD082

Other Parts Discussed in Thread: SN65MLVD082, SN65MLVD204B, SN65MLVD206B, SN65MLVD206, SN65MLVD200

art Number: SN65MLVD082

Dear Technical Support Team,

SN65MLVD082 datasheet shows it is possible to implement 32 nodes(max) with multipoint topology.

Could you share TI's result and topology of IBIS simulation for 32 nodes?

If you have the result  of other device like SN65MLVD204B and SN65MLVD206B, could you share them?

I'd like to know which do you simulate type1 or type2.

 Our customer has been trying IBIS simulation with 19 nodes, however their result  is not good.

So they'd like to refer TI's topology which is satisfied with 32 nodes.

■Condition of simulation

Node: 19 node

Termination register: 100Ω for the both ends

Line length : Approximately 420mm

Driver: Implement center of topology

Target IBIS model: SN65MLVD082

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/SN65MLVD082_5F00_IBIS-Model_5F00_SLLC174.zip

Simulation tool: signoise (Cadence)

 

Best Regards,

ttd

  • Hello ttd,

    We have assigned this post to a support engineer, so you should be getting a response soon.
    You might experience a longer response time because of the holidays this week.

    Regards,
    Jorge
  • Hi Jorge,

    Thank you for your reply.
    I'm looking forward to getting a response from a support engineer.

    Best Regards,
    ttd
  • Hi Jorge,

    Do you have any update so far?

    Best Regards,
    ttd
  • Hi,

    I can’t locate the 32 nodes simulation data on SN65MLVD082. There is a full load simulation at 100Mbps data on full 19 slots on SN65MLVD206 and SN65MLVD200. This is somehow close to your system requirement.

    The 19 nodes data shows good margin comparing to Type 2 spec. Attached is the file for the type 2 case on SN65MLVD206

    Type 2:

    30 Slot bp with type 2_waveforms.doc

    Below are the waveforms for the type 1 case on SN65MLVD200

    Type 1:

    Active Simulation example: slot 1 drives full 19 slots

    Active simulation example: slot 10 drives 19 full slots

    A non-monotonic rising or falling edge (i.e. an edge with a ripple) caused by reflections can have two important effects: (i) propagation delay extension (ii) wrong switching. If the extended propagation delay is still within the propagation delay budget, then it should be no concern. If the ripple on the rising edge goes as low as the VIL(max), or for the falling edge if it goes as high as the VIH(min) of the receiver, then wrong switching can happen.

    Regards,
    Dennis

  • Hi Dennis,

    Thank you for your reply and simulation results of TYPE1 and TYPE2.
    I understand that SN65MLVD200(TYPE1) has better margin than SN65MLVD206(TYPE2).

    I have additional questions below.

    1.)
    Could you show details of your topology?
    I'm happy if you provide your representative 19 node topology including schematics for TYPE1 and TYPE2.
    I'd like to refer these for our topology.

    2.)
    Your comment: This is somehow close to your system requirement.

    Does it mean following our condition when you simulated TYPE1 and TYPE2 ?

    ■Our condition
    Termination register: 100Ω for the both ends
    Line length : Approximately 420mm
    characteristic impedance of line: 100Ω
    Zdiff = 100Ω (L/S/L = 0.2mm/0.15mm/0.2mm、Thin(dielectric)=1.6mm

    3.)
    "Introduction to M-LVDS (TIA/EIA-899)" shows following difference between TYPE1 and TYPE2.
    Is it better to use both TYPE1 (data and clock) and TYPE2(control for failsafe)?
    TYPE2 has advantage for failsafe , but it has data rate limitation because of offset of threshold.

    --------------------------------------
    Type-1 receivers are expected to be used for maximum speed signals such as data or clock lines.
    Type-2 receivers are useful for lower speed applications such as control lines.

    www.ti.com/.../slla108a.pdf
    ⇒” 3.2.3 Input Thresholds and Type-1/Type-2 Receivers” on page.7.
    --------------------------------------

    Best Regards,
    ttd

  • Hi,

     

    Please contact the TI field apps support in your region. I have provided some documents to Ishida-san. He can review the block diagram with you.

     

    Node 19 and type 2 are your design requirements, is it corrected? This is what I see from your waveform. I have selected the similar simulation data which is closed to your design. The condition is not exactly the same as your setup. Please let me know if this is not the case.

     


     

    Can you elaborate more on your system requirement? What is your data rate?

     

    Dennis

  • Hi Dennis,

    Thank you for your schematic.
    I have just contacted TI's FAE.

    >Node 19 and type 2 are your design requirements
    ⇒ Yes , correct.
    Our customer would like to use data / clock with failsafe (only TYPE2).
    They don't consider to use TYPE1 now.

    >Can you elaborate more on your system requirement?
    ⇒I'll try to get schematic of customer's topology.
    I know only following condition. If you need more information , please let me know.

    Termination register: 100Ω for the both ends
    Line length : Approximately 420mm
    characteristic impedance of line: 100Ω
    Zdiff = 100Ω (L/S/L = 0.2mm/0.15mm/0.2mm、Thin(dielectric)=1.6mm

    >What is your data rate?
    ⇒ Current target is 40MHz(low = 12.5ns / High = 12.5ns).

    Best Regards,
    ttd

  • Hi Dennis,

    How do I check the margin of TYPE2 (50mV < VID < 150mV) from your attached waveform?

    Your waveform shows each input(VA and VB). I can judge the margin with Vid(differential input) following figures.

    30 Slot bp with type 2_waveforms.doc” including eight waves seems error on RX out except for 1th and 4th.

    Does this ”30 Slot bp with type 2_waveforms.doc” show the difficulties with TYPE2(100Mbps(50MHz)) with your system?

    My customer's target frequency is 40MHz with TYPE2.

    I'll discuss with TI FAE of my region next week.

    Best Regards,

    ttd

    Best Regards,

    ttd