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SN65LVDT388A: Single Ended Output of Differential Line Receiver

Patrick Ruf
Genius 4880 points
Part Number: SN65LVDT388A

Hi,

We have an application where we want to transmit data with up to 100Mbit/s with LVDS technology. Therefore we have chosen the SN65LVDT388A device. With a test board that connects the pin 35 (A1Y) to a Xilinx Artix-7 (AC701 board) we tested the signal integrity @ 100Mbit/s. Unfortunately the rising and falling edges  do not look very promising. Please see attached eye diagram CH1 (yellow signal). When I leave the output of the SN65LVDT388A open, the signal looks perfect. The input pin of the Xilinx Artix-7 is configured for LVTTL with 3.3V.
The distance between the SN65LVDT388A and the FPGA is about 8 inch. Any idea what could be the problem? Is it possible that reflections can lead to a signal like this?

Thanks and best regards,
Patrick

  • 0
    TI__Intellectual 1810 points
    Hi Patrick,

    Yes, reflections seem to cause the distortions on the rising and falling edges. Do you have the ability to use a series termination to help with impedance matching? Have you also probed at the Xilinx Artix-7 input? The signal there might be good enough for the FPGA to receive it without any errors.

    Best regards,

    Hassan.
  • 0 in reply to HA
    Genius 4880 points
    Hi Hassan,

    Yes I have tried it with a series resistor from 33 Ohm up to 100 Ohm. It does help a bit, especially with the 100 Ohm. But it looks as if signal level is close at its limit on the FPGA side with the 100 Ohm resistor. I did not tried yet to measure at the FPGA side as it is a bit more difficult but I will see what I can do. As I have routed the input data at the FPGA pin to an output pin of the FPGA I can see that the data is the same. So it should be received without errors but I do not know how close at the limit it might be. It would definitely be interesting how the signal quality is at the input of the FPGA. Thanks for the hint.

    Best regards,
    Patrick
  • 0 in reply to Patrick Ruf
    Genius 4880 points
    Hi Hassan,

    I did the measurement at the input of the FPGA. The signal looks much better on this side. Maybe I can reduce overshoot with a small series resistor on the SN65LVDT388A side.

    Best regards,
    Patrick
  • 0 in reply to Patrick Ruf
    TI__Intellectual 1810 points

    Hi Patrick,

    Great! Thanks for the update.

    Best regards,

    Hassan.